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EP2AGX65CU17I3N

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
Chapter 1: Overview for the Arria II Device Family 1–13
Arria II Device Architecture
July 2012 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration
■ Remote System Upgrade
■ Allows error-free deployment of system upgrades from a remote location
securely and reliably without an external controller
■ Soft logic (either the Nios II embedded processor or user logic) implementation
in the device helps download a new configuration image from a remote
location, store it in configuration memory, and direct the dedicated remote
system upgrade circuitry to start a reconfiguration cycle
■ Dedicated circuitry in the remote system upgrade helps to avoid system down
time by performing error detection during and after the configuration process,
recover from an error condition by reverting back to a safe configuration
image, and provides error status information
SEU Mitigation
■ Offers built-in error detection circuitry to detect data corruption due to soft errors
in the configuration random access memory (CRAM) cells
■ Allows all CRAM contents to be read and verified to match a
configuration-computed cyclic redundancy check (CRC) value
■ You can identify and read out the bit location and the type of soft error through the
JTAG or the core interface
JTAG Boundary Scan Testing
■ Supports JTAG IEEE Std. 1149.1 and IEEE Std. 1149.6 specifications
■ IEEE Std. 1149.6 supports high-speed serial interface (HSSI) transceivers and
performs boundary scan on alternating current (AC)-coupled transceiver channels
■ Boundary-scan test (BST) architecture offers the capability to test pin connections
without using physical test probes and capture functional data while a device is
operating normally
1–14 Chapter 1: Overview for the Arria II Device Family
Reference and Ordering Information
Arria II Device Handbook Volume 1: Device Interfaces and Integration July 2012 Altera Corporation
Reference and Ordering Information
Figure 1–3 shows the ordering codes for Arria II devices.
Document Revision History
Table 1–10 lists the revision history for this chapter.
Figure 1–3. Packaging Ordering Information for Arria II Devices
Device Density
Packa
g
eTyp
e
3, 4, 5, or 6, with 3 being the fastest
Corresponds to pin count
17 = 358 pins
25 = 572 pins
29 = 780 pins
35 = 1152 pins
40 = 1517 pins
F: FineLine BGA (FBGA)
U: Ultra FineLine BGA (UBGA)
H: Hybrid FineLine BGA (HBGA)
GX: 45, 65, 95, 125, 190,260
GZ: 225, 300, 350
Optional SuffixFa m i l y S i g n a t u r e
Operating Temperature
Sp e e d G r a d e
Ball Array Dimension
4
EP2AGX
45
C
17
F
N
Indicates specific device options
N: Lead-free devices
ES: Engineering sample
EP2AGX
EP2AGZ
C
Transceiver Count
C: 4
D: 8
E: 12
F:16
H: 24
C: Commercial temperature (t
J
= 0°C to 85°C)
I: Industrial temperature (t
J
= -40°C to 100°C)
Table 1–10. Document Revision History (Part 1 of 2)
Date Version Changes
July 2012 4.4
Replaced Table 1-10. External Memory Interface Maximum Performance for Arria II Devices
with link to the External Memory Interface Spec Estimator online tool.
December 2011 4.3 Updated Table 1–4 and Table 1–9.
June 2011 4.2 Updated Table 1–2.
June 2011 4.1
■ Updated Figure 1–2.
■ Updated Table 1–10.
■ Updated the “Arria II Device Feature” section.
■ Added Table 1–6.
■ Minor text edits.
December 2010 4.0
■ Updated for the Quartus II software version 10.0 release
■ Added information about Arria II GZ devices
■ Updated Table 1–1, Table 1–4, Table 1–5, Table 1–6, Table 1–7, and Table 1–9
■ Added Table 1–3
■ Added Figure 1–2
■ Updated Figure 1–3
■ Updated “Arria II Device Feature” and “Arria II Device Architecture” section
Chapter 1: Overview for the Arria II Device Family 1–15
Document Revision History
July 2012 Altera Corporation Arria II Device Handbook Volume 1: Device Interfaces and Integration
July 2010 3.0
Updated for the Quartus II software version 10.0 release:
■ Added information about –I3 speed grade
■ Updated Table 1–1, Table 1–3, and Table 1–7
■ Updated Figure 1–2
■ Updated “Highlights” and “High-Speed LVDS I/O and DPA”section
■ Minor text edits
November 2009 2.0
■ Updated Table 1–1, Table 1–2, and Table 1–3
■ Updated “Configuration Features” section
June 2009 1.1
■ Updated Table 1–2.
■ Updated “I/O Features” section.
February 2009 1.0 Initial release.
Table 1–10. Document Revision History (Part 2 of 2)
Date Version Changes
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EP2AGX65CU17I3N

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