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LT1969CMS#PBF

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10
LT1969
Input Considerations
The inputs of the LT1969 are an NPN differential pair
protected by back-to-back diodes (see the Simplified
Schematic). There are no series protection resistors
onboard which would degrade the input voltage noise. If
the inputs can have a voltage difference of more than 0.7V,
the input current should be limited to less than 10mA with
external resistance (usually the feedback resistor or source
resistor). Each input also has two ESD clamp diodes—one
to each supply. If an input drive exceeds the supply, limit
the current with an external resistor to less than 10mA.
The LT1969 design is a true operational amplifier with high
impedance inputs and low input bias currents. The input
offset current is a factor of ten lower than the input bias
current. To minimize offsets due to input bias currents,
match the equivalent DC resistance seen by both inputs.
The low input noise current can significantly reduce total
noise compared to a current feedback amplifier, especially
for higher source resistances.
Layout and Passive Components
With a gain bandwidth product of 700MHz the LT1969
requires attention to detail in order to extract maximum
performance. Use a ground plane, short lead lengths and
a combination of RF-quality supply bypass capacitors
(i.e., 470pF and 0.1µF). As the primary applications have
high drive current, use low ESR supply bypass capacitors
(1µF to 10µF). For best distortion performance with high
drive current a capacitor with the shortest possible trace
lengths should be placed between Pins 1 and 5. The
optimum location for this capacitor is on the back side of
the PC board.
The parallel combination of the feedback resistor and gain
setting resistor on the inverting input can combine with
the input capacitance to form a pole which can cause
frequency peaking. In general, use feedback resistors of
1kΩ or less.
Thermal Issues
The LT1969 enhanced θ
JA
MS10 package has the V
–
pin
fused to the lead frame. This thermal connection increases
the efficiency of the PC board as a heat sink. The PCB
material can be very effective at transmitting heat between
the pad area attached to the V
–
pin and a ground or power
plane layer. Copper board stiffeners and plated through-
holes can also be used to spread the heat generated by the
device. Table 1 lists the thermal resistance for several
different board sizes and copper areas. All measurements
Large-Signal Transient, A
V
= 10,
Low Power**
Large-Signal Transient, A
V
= –10,
Low Power**
1969 G41
1969 G42
APPLICATIO S I FOR ATIO
WUUU
TYPICAL PERFOR A CE CHARACTERISTICS
UW
*13k RESISTOR FROM CTRL1 TO V
–
AND A 49.9k RESISTOR FROM CTRL2 TO V
–
** 49.9k RESISTOR FROM CTRL2 TO V
–
, CTR1 FLOATING
11
LT1969
were taken in still air on 3/32" FR-4 board with 2oz copper.
This data can be used as a rough guideline in estimating
thermal resistance. The thermal resistance for each appli-
cation will be affected by thermal interactions with other
components as well as board size and shape.
Table 1. Fused 10-Lead MSOP Package
COPPER AREA
TOPSIDE* BACKSIDE BOARD AREA THERMAL RESISTANCE
(mm
2
)(mm
2
)(mm
2
) (JUNCTION-TO-AMBIENT)
540 540 2500 110°C/W
100 100 2500 120°C/W
100 0 2500 130°C/W
30 0 2500 135°C/W
0 0 2500 140°C/W
*Device is mounted on topside.
Calculating Junction Temperature
The junction temperature can be calculated from the
equation:
T
J
= (P
D
)(θ
JA
) + T
A
T
J
= Junction Temperature
T
A
= Ambient Temperature
P
D
= Device Dissipation
θ
JA
= Thermal Resistance (Junction-to-Ambient)
As an example, calculate the junction temperature for the
circuit in Figure 1 assuming an 70°C ambient temperature.
The device dissipation can be found by measuring the
supply currents, calculating the total dissipation and then
subtracting the dissipation in the load.
The dissipation for the amplifiers is:
P
D
= (63.5mA)(12V) – (4V/√2)
2
/(50) = 0.6W
The total package power dissipation is 0.6W. When a 2500
sq. mm PC board with 540 sq. mm of 2oz copper on top
and bottom is used, the thermal resistance is 110°C/W.
The junction temperature T
J
is:
T
J
= (0.6W)(110°C/W) + 70°C = 136°C
The maximum junction temperature for the LT1969 is
150°C so the heat sinking capability of the board is
adequate for the application.
If the copper area on the PC board is reduced to 0 sq. mm
the thermal resistance increases to 140°C/W and the
junction temperature becomes:
T
J
= (0.6W)(140°C/W) + 70°C = 154°C
which is above the maximum junction temperature indi-
cating that the heat sinking capability of the board is
inadequate and should be increased.
APPLICATIO S I FOR ATIO
WUUU
Figure 1. Thermal Calculation Example
–
+
6V
–6V–6V –6V
909Ω
100Ω
100Ω
–
+
1969 F01
1K
50Ω
–4V
4V
f = 1MHz
13k
6
49.9k
CTRL1 CTRL2
7
12
LT1969
Capacitive Loading
The LT1969 is stable with a 1000pF capacitive load. The
photo of the small-signal response with 1000pF load in a
gain of 10 shows 50% overshoot. The photo of the large-
signal response with a 1000pF load shows that the output
slew rate is not limited by the short-circuit current. The
Typical Performance Curve of Frequency Response vs
Capacitive Load shows the peaking for various capacitive
loads.
This stability is useful in the case of directly driving a
coaxial cable or twisted pair that is inadvertently
unterminated. For best pulse fidelity, however, a termina-
tion resistor of value equal to the characteristic impedance
of the cable or twisted pair (i.e., 50Ω/75Ω/100Ω/135Ω)
should be placed in series with the output. The other end
of the cable or twisted pair should be terminated with the
same value resistor to ground.
APPLICATIO S I FOR ATIO
WUUU
Figure 2. Compensation for Inverting Gains
R
G
R
C
V
o
V
i
C
C
(OPTIONAL)
–
+
1969 F02
R
F
=
–R
F
R
G
V
o
V
i
< 15MHz
1
2πR
C
C
C
(R
C
|| R
G
) ≤ R
F
/9
Figure 3. Compensation for Noninverting Gains
R
C
V
o
V
i
C
C
(OPTIONAL)
+
–
1969 F03
R
F
R
G
= 1 +
R
F
R
G
V
o
V
i
< 15MHz
1
2πR
C
C
C
(R
C
|| R
G
) ≤ R
F
/9
Compensation
The LT1969 is stable in a gain 10 or higher for any supply
and resistive load. It is easily compensated for lower gains
with a single resistor or a resistor plus a capacitor.
Figure␣ 2 shows that for inverting gains, a resistor from the
inverting node to AC ground guarantees stability if the
parallel combination of R
C
and R
G
is less than or equal to
R
F
/9. For lowest distortion and DC output offset, a series
capacitor, C
C
, can be used to reduce the noise gain at lower
frequencies. The break frequency produced by R
C
and C
C
should be less than 15MHz to minimize peaking. The
Typical Curve of Frequency Response vs Supply Voltage,
A
V
= –1 shows less than 1dB of peaking for a break
frequency of 12.8MHz.
Figure 3 shows compensation in the noninverting configu-
ration. The R
C
, C
C
network acts similarly to the inverting
case. The input impedance is not reduced because the
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LT1969CMS#PBF

Mfr. #:
Buy LT1969CMS#PBF
Manufacturer:
Analog Devices Inc.
Description:
High Speed Operational Amplifiers 700MHz Dual 200mA OA with programmable I supply in MS10
Lifecycle:
New from this manufacturer.
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