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74F825
Unit Loading/Fan Out
Functional Description
The 74F825 consists of eight D-type edge-triggered
flip-flops. This device has 3-STATE true outputs and is
organized in broadside pinning. In addition to the clock and
output enable pins, the buffered clock (CP) and buffered
Output Enable (OE
) are common to all flip-flops. The
flip-flops will store the state of their individual D inputs that
meet the setup and hold times requirements on the
LOW-to-HIGH CP transition. With the OE
LOW the con-
tents of the flip-flops are available at the outputs. When the
OE
is HIGH, the outputs go to the high impedance state.
Operation of the OE
input does not affect the state of the
flip-flops. The 74F825 has Clear (CLR
) and Clock Enable
(EN
) pins.
When the CLR
is LOW and the OE is LOW the outputs are
LOW. When CLR
is HIGH, data can be entered into the
flip-flops. When EN
is LOW, data on the inputs is trans-
ferred to the outputs on the LOW-to-HIGH clock transition.
When the EN
is HIGH the outputs do not change state,
regardless of the data or clock input transitions.
Function Table
L = LOW Voltage Level Z = High Impedance
H = HIGH Voltage Level
= LOW-to-HIGH Transition
X = Immaterial NC = No Change
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Pin Names Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
D
0
–D
7
Data Inputs 1.0/1.0 20 µA/−0.6 mA
O
0
–O
7
3-STATE Data Outputs 150/40 (33.3) −3 mA/24 mA (20 mA)
OE
1
, OE
2
, OE
3
Output Enable Input 1.0/1.0 20 µA/−0.6 mA
EN
Clock Enable 1.0/1.0 20 µA/−0.6 mA
CLR
Clear 1.0/1.0 20 µA/−0.6 mA
CP Clock Input 1.0/2.0 20
µA/−1.2 mA
Inputs Internal Output
Function
OE
CLR EN CP D Q O
HHLHXNC Z Hold
HHLLXNC Z Hold
H H H X X NC Z Hold
LHHXXNC NCHold
H L X X X H Z Clear
L L X X X H L Clear
HHL
L H Z Load
HHL
H L Z Load
LHL
L H L Data Available
LHL
H L H Data Available
L H L H X NC NC No Change in Data
L H L L X NC NC No Change in Data
