87016AYLFT Datasheet 87016AYLF, 87016AYLFT, 87016AYLF/W | P1-P3

Low Skew, 1-to-16

LVCMOS/LVTTL Clock Generator

87016

DATASHEET

GENERAL DESCRIPTION

The 87016 is a low skew, 1:16 LVCMOS/LVTTL Clock Generator.

The device has 4 banks of 4 outputs and each bank can be

independently selected for ÷1 or ÷2 frequency operation. Each

bank also has its own power supply pins so that the banks can

operate at the following different voltage levels: 3.3V, 2.5V, and

1.8V. The low impedance LVCMOS/LVTTL outputs are designed

to drive 50Ω series or parallel terminated transmission lines.

The divide select inputs, DIV_SELA:DIV_SELD, control the

output frequency of each bank. The output banks can be

independently selected for ÷1 or ÷2 operation. The bank enable

inputs, CLK_ENA:CLK_END, support enabling and disabling

each bank of outputs individually. The CLK_ENA:CLK_END

circuitry has a synchronizer to prevent runt pulses when

enabling or disabling the clock outputs. The master reset

input, nMR/OE, resets the ÷1/÷2 ﬂ ip ﬂ ops and also controls the

active and high impedance states of all outputs. This pin has

an internal pull-up resistor and is normally used only for test

purposes or in systems which use low power modes.

The 87016 is characterized to operate with the core at

3.3V and the banks at 3.3V, 2.5V, or 1.8V. Guaranteed

bank, output, and part-to-part skew characteristics make

the 87016 ideal for those clock applications demanding

well-deﬁ ned performance and repeatability.

FEATURES

• Sixteen LVCMOS/LVTTL outputs (4 banks of 4 outputs)

• Selectable differential CLK1, nCLK1 or

LVCMOS clock input

• CLK1, nCLK1 pair can accept the following differential input

levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL

• CLK0 supports the following input types:

LVCMOS, LVTTL

• Maximum output frequency: 250MHz

• Independent bank control for ÷1 or ÷2 operation

• Independent output bank voltage settings for 3.3V, 2.5V,

or 1.8V operation

• Asynchronous clock enable/disable

• Output skew: 170ps (maximum)

• Bank skew: 30ps (maximum)

• Part-to-part skew: 750ps (maximum)

• 3.3V core, 3.3V, 2.5V, or 1.8V output operating supply

• 0°C to 85°C ambient operating temperature

• Available in lead-free RoHS compliant package

BLOCK DIAGRAM PIN ASSIGNMENT

48-Pin LQFP

7mm x 7mm x 1.4mm body package

Y Package

Top View

LOW SKEW, 1-TO-16

LVCMOS/LVTTL CLOCK GENERATOR

87016 DATA SHEET

2 REVISION C 06/26/15

TABLE 1. PIN DESCRIPTIONS

Number Name Type Description

1, 48 V

Power Positive supply pins.

2 CLK0 Input Pulldown LVCMOS / LVTTL clock input.

3 DIV_SELA Input Pullup

Controls frequency division for Bank A outputs.

LVCMOS / LVTTL interface levels.

4 DIV_SELB Input Pullup

Controls frequency division for Bank B outputs

LVCMOS / LVTTL interface levels..

5 DIV_SELC Input Pullup

Controls frequency division for Bank C outputs.

LVCMOS / LVTTL interface levels.

6 DIV_SELD Input Pullup

Controls frequency division for Bank D outputs.

LVCMOS / LVTTL interface levels.

7 CLK_ENA Input Pullup

Output enable for Bank A outputs. Active HIGH.

If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.

8 CLK_ENB Input Pullup

Output enable for Bank B outputs. Active HIGH.

If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.

9 CLK_ENC Input Pullup

Output enable for Bank C outputs. Active HIGH.

If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.

10 CLK_END Input Pullup

Output enable for Bank D outputs. Active HIGH.

If pin is LOW, outputs drive low. LVCMOS / LVTTL interface levels.

11 nMR/OE Input Pullup

Master reset. When LOW, resets the ÷1/÷2 ﬂ ip ﬂ ops and sets the

outputs to high impedance. LVCMOS / LVTTL interface levels.

12, 16, 20, 24, 28,

32, 36, 40, 44

GND Power Power supply ground.

13, 15, 17, 19

QD3, QD2,

QD1, QD0

Output Bank D outputs. LVCMOS / LVTTL interface levels.

14, 18 V

DDOD

Power Output Bank D power supply pins.

21, 23, 25, 27

QC3, QC2,

QC1, QC0

Output Bank C outputs. LVCMOS / LVTTL interface levels.

22, 26 V

DDOC

Power Output Bank C power supply pins.

29, 31, 33, 35

QB3, QB2,

QB1, QB0

Output Bank B outputs. LVCMOS / LVTTL interface levels.

30, 34 V

DDOB

Power Output Bank B power supply pins.

37, 39, 41, 43

QA3, QA2,

QA1, QA0

Output Bank A outputs. LVCMOS / LVTTL interface levels.

38, 42 V

DDOA

Power Output Bank A power supply pins.

45 CLK_SEL Input Pulldown

Clock select input. When HIGH, selects CLK1, nCLK1 inputs.

When LOW, selects CLK0 input. LVCMOS / LVTTL interface levels.

46 nCLK1 Input Pullup Inverting differential clock input.

47 CLK1 Input Pulldown Non-inverting differential clock input.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

REVISION C 06/26/15

87016 DATA SHEET

3 LOW SKEW, 1-TO-16

LVCMOS/LVTTL CLOCK GENERATOR

TABLE 2. PIN CHARACTERISTICS

TABLE 3. FUNCTION TABLE

Inputs Outputs

nMR/OE CLK_ENx DIV_SELx Bank X Qx Frequency

0 X X Hi Z N/A

1 1 0 Active fIN/2

1 1 1 Active fIN

1 0 X Low N/A

Symbol Parameter Test Conditions Minimum Typical Maximum

Units

Input Capacitance 4 pF

PULLUP

Input Pullup Resistor 51

kΩ

Power Dissipation Capacitance

(per output); NOTE 1

, V

DDOx

= 3.465V 18 pF

= 3.465, V

DDOx

= 2.625V 20 pF

= 3.465, V

DDOx

= 1.89V 30 pF

OUT

Output Impedance 7

NOTE 1: V

DDOx

denotes V

DDOA

, V

DDOB

, V

DDOC

, and V

DDOD

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P17

87016AYLFT

Mfr. #:

Buy 87016AYLFT

Manufacturer:

IDT

Description:

Clock Generators & Support Products 16 LVCMOS OUT BUFFER/DIVIDER

Lifecycle:

New from this manufacturer.

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87016AYLFT

87016AYLFT

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