BU1572GUW, BU1573KV, BU1574KU
Technical Note
9/12
www.rohm.com
2009.04- Rev.B
© 2009 ROHM Co., Ltd. All rights reserved.
2. RGB interface
2.1. RGB interface timing
The input timing of image signal on RGB I/F is shown in Table 2.1-1.
The output timing of image signal on RGB I/F is shown in Table 2.1-2.
Symbol Explanation MIN. TYP. MAX. UNIT
t
DCLK
Clock Cycle 27.7 - - ns
d
DCLK
Clock Duty 40 50 60 %
t
ODD
Decision of LCDDO from DCKO - - 5 ns
t
OCD
Decision of LCDVSO or LCDHSO from DCKO - - 5 ns
3. YUV interface
3.1. YUV interface timing
The input timing of image signal on YUV I/F is shown in Table 3.1-1.
The output timing of image signal on YUV I/F is shown in Table 3.1-2.
Symbol Explanation MIN. TYP. MAX
UN
t
DS
Camera setup period
(between the DCKI rising and falling edges)
8 - - ns
t
DH
Camera holding period
(between the DCKI rising and falling edges)
8 - – ns
Symbol Explanation MIN.
TYP
MAX
UNI
t
DS
Camera setup period
(between the CAMCKI rising and falling edges)
8 - - ns
t
DH
Camera holding period
(between the CAMCKI rising and falling edges)
8 - – ns
Symbol Explanation MIN. TYP. MAX. UNIT
t
PCLK
Clock Cycle 27.7 - - ns
d
PCLK
Clock Duty 40 50 60 %
t
ODD
Decision of CAMDO from CAMCKO - - 5 ns
t
OCD
Decision of CAMVSO or CAMHSO from CAMCKO - - 5 ns
Table 2.1-1 BU1572GUW/BU1573KV RGB interface in
ut timin
Table 2.1-2 BU1572GUW/BU1573KV Image signal output timing
LCDVSI
LCDHSI
LCDDI0
－LCDDI17
DCKI
(CKPOL=“0”)
DCKI
(CKPOL=“1”)
t
DS
t
DH
LCDVSO
LCDDO
[17:0]
LCDHSO
DCKO
t
DCLK
t
OCD
t
OCD
t
ODD
Table 3.1-1 BU1574KU YUV interface in
ut timin
CAMVSI
CAMHSI
CAMDI0
－CAMDI7
CAMCKI
(CKPOL=“1”)
CAMCKI
(CKPOL=“0”)
t
DS
t
DH
Table 3.1-2 BU1574KU Image signal output timing
CAMVSO
CAMDO[7:0]
CAMHSO
CAMCKO
t
PCLK
t
OCD
t
OCD
t
ODD
