50 MHz to 125 MHz
±20ppm APR Min
0°C to 70°C
-40°C to 85°C
-45°C to 90°C
3.3V ±0.3V
1.65V ±1.65V
88mA Max
Differential LVPECL
45/55% Max @ 50% Vcc
1ns Max @ 20% to 80% Vcc
±10% Max
Terminated to Vcc-2V into 50 ohms
"0" = Vcc-1.85V Min, Vcc-1.62V Max
"1" = Vcc-1.02V Min, Vcc-0.81V Max
200ns
1ms Typical, 2ms Max
0.5psec Typical, 1psec RMS Max
-65 dBc/Hz Typical
-98 dBc/Hz Typical
-125 dBc/Hz Typical
-140 dBc/Hz Typical
-145 dBc/Hz Typical
<3ppm 1
st
year, <1ppm every year thereafter
Frequency Range:
Frequency Pulling:
Temperature Range:
(Option X)
Storage:
Input Voltage:
Control Voltage:
Input Current:
Output:
Symmetry:
Rise/Fall Time:
Linearity:
Logic:
Disable Time:
Start-up Time:
Phase Jitter: 12kHz to 80MHz
Phase Noise: 10Hz
100Hz
1kHz
10kHz
100kHz
Aging:
Specifications subject to change without notice.
RECOMMENDED REFLOW SOLDERING PROFILE
217°C
200°C
260°C
150°C
90 Secs. Max.
TEMPERATURE
Ramp-Up
3°C/Sec Max.
Preheat
180 Secs. Max.
8 Minutes Max.
260°C for
10 Secs. Max.
Critical
Temperature Zone
Ramp-Down
6°C/Sec.
NOTE: Reflow Profile with 240°C peak also acceptable.
TD-030701 Rev. G
9×14 mm SMD, 3.3V, LVPECL
CVPD-920 Model
0.360
(9.14)
0.560
(14.2)
CRYSTEK
P/N
Frequency
Date Code
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: 239-561-3311 • 800-237-3061
Fax: 239-561-1025 • www.crystek.com
CRYSTEK
CORPORATION
SUGGESTED PAD LAYOUT
0.280
(7.11)
0.050
(1.27)
0.090
(2.28)
0.200
(5.08)
0.210
(5.3)
0.560
(14.2)
Designed to meet today's requirements for
3.3V Differential LVPECL applications.
The CVPD-920 is produced using our cost
saving FR5 PCB and UM-1 overtone
crystal technology. This design offers
considerable cost savings over other HFF
VCXO products when broad frequency
pulling is not required. Also available in 14
pin dip fully hermetic package.
CVPD-920 X - 100.000
Crystek Part Number Guide
#1 Crystek 9×14 SMD PECL VCXO
#2 Model 920
#3 Temp. Range: Blank = 0/70°C, X = -40/85°C
#4 Frequency in MHz: 3 or 6 decimal places
#1 #2 #3 #4
Example:
CVPD-920X-100.000 = 3.3V, 45/55, -40/85°C, 100.000 MHz
PIN Function
1
2
3
4
5
6
Control Volt
E/D
GND
OUT
COUT
Vcc
Pin 2 Output Pin
Open
"0" level Vcc-1.620V Max
"1" level Vcc-1.025V Min
Active
Active
Disabled
Enable/Disable Function
Disabled State:
Pin 4 will assume a fixed level of logic "0"
Pin 5 will assume a fixed level of logic "1"
0.200
(5.08)
0.040
(1.01)
0.070
(1.77)
1
46
2 3
5
0.100
(2.54)
