© Semiconductor Components Industries, LLC, 2006
June, 2006 − Rev. 8
1 Publication Order Number:
MC14555B/D
MC14555B, MC14556B
Dual Binary to 1−of−4
Decoder/Demultiplexer
The MC14555B and MC14556B are constructed with
complementary MOS (CMOS) enhancement mode devices. Each
Decoder/Demultiplexer has two select inputs (A and B), an active low
Enable input (E), and four mutually exclusive outputs (Q0, Q1, Q2,
Q3). The MC14555B has the selected output go to the “high” state,
and the MC14556B has the selected output go to the “low” state.
Expanded decoding such as binary−to−hexadecimal (1−of−16), etc.,
can be achieved by using other MC14555B or MC14556B devices.
Applications include code conversion, address decoding, memory
selection control, and demultiplexing (using the Enable input as a data
input) in digital data transmission systems.
Features
• Diode Protection on All Inputs
• Active High or Active Low Outputs
• Expandable
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• All Outputs Buffered
• Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load Over the Rated Temperature Range
• Pb−Free Packages are Available*
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Parameter
Symbol Value Unit
DC Supply Voltage Range V
DD
−0.5 to +18.0 V
Input or Output Voltage Range
(DC or Transient)
V
in
, V
out
−0.5 to V
DD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
I
in
, I
out
± 10 mA
Power Dissipation, per Package (Note 1) P
D
500 mW
Ambient Temperature Range T
A
−55 to +125 °C
Storage Temperature Range T
stg
−65 to +150 °C
Lead Temperature (8−Second Soldering) T
L
260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/°C From 65°C To 125°C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
v (V
in
or V
out
) v V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
x = 5 or 6
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G = Pb−Free Package
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B
1
16
1455xBG
AWLYWW
SOEIAJ−16
F SUFFIX
CASE 966
1
16
MC1455xB
ALYWG
16
1
MC1455xBCP
AWLYYWWG
1
1
1
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q0
B
B
B
A
B
E
B
V
DD
Q3
B
Q2
B
Q1
B
Q0
A
B
A
A
A
E
A
V
SS
Q3
A
Q2
A
Q1
A
MC14555B
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q
0
B
B
B
A
B
E
B
V
DD
Q3
B
Q2
B
Q1
B
Q0
A
B
A
A
A
E
A
V
SS
Q3
A
Q2
A
Q1
A
MC14556B
PIN ASSIGNMENTS
