LTC4054LES5-4.2#TRMPBF

LTC4054L-4.2
13
4054l42fa
When the battery is nearing full charge, the charger enters
the constant-voltage portion of the charge cycle and the
charge current begins to drop. When the charge current
drops below 1/10 of the programmed current, the charge
cycle ends, and the strong pull-down is replaced by the
20µA pull-down, indicating that the charge cycle has
ended. If the input voltage is removed or drops below the
undervoltage lockout threshold, the CHRG pin becomes
high impedance. Figure 3 shows that by using two differ-
ent value pull-up resistors, a microprocessor can detect
all three states from this pin.
To detect when the LTC4054L is in charge mode, force the
digital output pin (OUT) high and measure the voltage at
the CHRG pin. The N-channel MOSFET will pull the pin
voltage low even with the 2k pull-up resistor. Once the
charge cycle terminates, the N-channel MOSFET is turned
off and a 20µA current source is connected to the CHRG
pin. The IN pin will then be pulled high by the 2k pull-up
resistor. To determine if there is a weak pull-down current,
the OUT pin should be forced to a high impedance state.
The weak current source will pull the IN pin low through the
800k resistor; if CHRG is high impedance, the IN pin will
be pulled high, indicating that the part is in a UVLO state.
Reverse Polarity Input Voltage Protection
In some applications, protection from reverse polarity volt-
age on V
CC
is desired. If the supply voltage is high enough,
a series blocking diode can be used. In other cases, where
the voltage drop must be kept low a P-channel MOSFET
can be used (as shown in Figure 4).
USB and Wall Adapter Power
The LTC4054L allows charging from both a wall adapter
and a USB port. Figure 5 shows an example of how to
combine wall adapter and USB power inputs. A P-channel
MOSFET, MP1, is used to prevent back conducting into the
USB port when a wall adapter is present and a Schottky
diode, D1, is used to prevent USB power loss through the
1k pull-down resistor.
Figure 3. Using a Microprocessor to Determine CHRG State
CHRG OUT
IN
2k
800k
4054L42 F03
LTC4054L µPROCESSOR
V
+
V
DD
V
CC
Figure 4. Low Loss Input Reverse Polarity Protection
Figure 5. Combining Wall Adapter and USB Power
V
IN
V
CC
LTC4054L
DRAIN-BULK
DIODE OF FET
4054L42 F04
+
LTC4054L-4.2
PROG
V
CC
D1
5V WALL
ADAPTER
USB
POWER
100mA
SYSTEM
LOAD
Li-Ion
BATTERY
MP1
1k 1.5k
4
3
5
4054l42 F05
BAT
applicaTions inForMaTion
LTC4054L-4.2
14
4054l42fa
package DescripTion
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45 TYP
5 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3)
S5 TSOT-23 0302 REV B
PIN ONE
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX
0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
S5 Package
5-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1635)
LTC4054L-4.2
15
4054l42fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
revision hisTory
REV DATE DESCRIPTION PAGE NUMBER
A 8/11 Corrected lead count on last bullet item in Features. 1

LTC4054LES5-4.2#TRMPBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Battery Management Monlithic Li-Ion Charger - low current
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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