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STGIPS14K60
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
Electrical ch
aracteristics
STGIPS14K60
10/21
DocID15927 Rev 9
Note:
X: don’t car
e
T
able 1
1. Sen
se comparator characterist
ics (V
CC
= 15 V unles
s otherwise spe
cified)
Symbol
Pa
rameter
T
est conditions
Min.
T
yp.
Max.
Unit
I
ib
Input bias current
V
CIN
= 1 V
3
µ
A
V
ol
Open drain low level output
voltage
I
od
= 3 mA
0.5
V
t
d_comp
Comparator delay
SD/OD pulled to 5 V through
100 k
Ω
resistor
90
130
ns
SR
Sl
ew rate
C
L
= 180 pF; R
pu
= 5 k
Ω
60
V/µsec
t
sd
Shut down to high / low side
driver propagation delay
V
OUT
= 0, V
boo
t
= V
CC
,
V
IN
= 0 to 3.3 V
50
125
200
ns
t
isd
Comparator triggering to
high /
low side driver turn-of
f
propagation delay
Measured applying a voltage
step from 0 V to 3.3 V to pin
CIN
i
50
200
250
T
ab
le 12. T
ru
th ta
ble
Condition
Logic input (V
I
)
Output
SD/OD
LIN
HIN
L
VG
HVG
Shutdown enable
half-bridge tri-stat
e
L
X
X
L
L
Interlocking
half-bridge tri-stat
e
H
L
H
L
L
0 ‘’logic state”
half-bridge tri-stat
e
H
H
L
L
L
1 “logic state”
low side direct driving
H
L
L
H
L
1 “logic state”
high side direct driving
H
H
H
L
H
DocID15927 Rev 9
1
1/21
STGIPS14K60
Electrical ch
aracteristics
21
Figure
5.
Maximum
I
C(RMS
)
current
vs
.
switching
frequency
(1)
Figure 6. Maximu
m I
C(RMS
)
current vs. f
SINE
(1)
1.
Simula
ted curv
es refer
to typi
cal IGBT
paramete
rs and
maxim
um R
thj-c.
8
10
12
14
16
18
4
6
8
10
12
14
16
18
I
c(R
M
S)
[A]
f
sw
[kHz]
V
PN
= 300
V, Modulation
index
=
0.8,
PF
=
0.6, T
j
= 15
0
°
C, f
SINE
= 60
Hz
Tc = 80 °C
Tc = 100 °C
6
7
8
9
10
11
1
10
I
c(R
M
S)
[A]
f
SINE
[Hz]
fsw
=
12 kHz
fsw
=
20 kHz
fsw
=
16 kHz
V
PN
= 300
V, Modulation
index
=
0.8,
PF
=
0.6, T
j
= 15
0
°
C, T
c
= 10
0
°
C
Electrical ch
aracteristics
STGIPS14K60
12/21
DocID15927 Rev 9
3.2
W
a
veform
defin
itions
Figure 7. Dead
time and in
terlocking wavef
orms definit
ions
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
LIN
HIN
LVG
HVG
DT
LH
DT
HL
DT
LH
DT
HL
DT
LH
DT
HL
DT
LH
DT
HL
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
INTERLOCKING
INTERLOCKING
CONTROL SIGNAL
EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD
TIME:
DEAD TIME
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
(*) HIN and LIN can be connected together and driven b
y just one control signal
INTERLOCKING
INTERLOCKING
G
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
STGIPS14K60
Mfr. #:
Buy STGIPS14K60
Manufacturer:
STMicroelectronics
Description:
IGBT Modules Intelligent Pwr Mod 600V 12A 3Phase IGBT
Lifecycle:
New from this manufacturer.
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