LT4256-1/LT4256-2
9
425612fa
APPLICATIO S I FOR ATIO
WUU
U
Figure 5. 1600mA, 48V Application
Figure 6. Start-Up Waveforms
When the power pins first make contact, transistor Q1 is
held off. If the voltage on V
CC
is above the externally
programmed undervoltage threshold, V
CC
is above 9.8V,
and the voltage on TIMER is less than 4.65V (typ), transis-
tor Q1 will be turned on (Figure 6). The voltage on GATE
rises with a slope equal to 32µA/C1 and the supply inrush
current is set at:
I
INRUSH
= C
L
• 32µA/C1 (1)
where C
L
is the total load capacitance.
To reduce inrush current, increase C1 or decrease load
capacitance. If the voltage across the current sense resis-
tor R5 reaches V
SENSETRIP
, the inrush current will be
limited by the internal current limit circuitry. The voltage
on GATE is adjusted to maintain a constant voltage across
the sense resistor and TIMER begins to charge.
When the FB voltage goes above the low-to-high V
FB
threshold, PWRGD goes high.
Undervoltage Detection
The LT4256-1/LT4256-2 uses UV to monitor the V
CC
voltage to determine when it is safe to turn on the load and
allow the user the greatest flexibility for setting the thresh-
old. Any time that UV goes below 3.6V, GATE will be pulled
low until UV goes above 4V again.
The UV threshold should never be set below the internal
UVLO threshold (9.8V typically) because the benefit of
UV’s hysteresis will be lost, making the LT4256-1/
4256 F05
R5
0.025Ω
LT4256-1/
LT4256-2
SENSE
6
2
3
4
87
1
5
V
CC
GATE
FB
PWRGD
UV
TIMER
GND
V
IN
48V
GND
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R2
8.06k
R1
64.9k
R7
100Ω
R9
4.02k
R6
10Ω
R8
36.5k
PWRGD
V
OUT
48V
1.6A
R4
27k
C
L
C2
33nF
C3
0.1µF
C1
10nF
D2
SMAT70A
UV = 36V
PWRGD = 40V
+
LT4256-2 more susceptible to noise (V
CC
must be at least
9.8V when UV is at its 3.6V threshold). UV is filtered with
C3 to prevent noise spikes and capacitively coupled glitches
from shutting down the LT4256-1/LT4256-2 output
erroneously.
To calculate the UV threshold, use the following equations:
RR
V
V
kRR k
V
R
R
THUVLH
THUVLH
12
4
1
20 1 2 200
36 1
1
2
= −
⎛
⎝
⎜
⎞
⎠
⎟
Ω≤ + ≤Ω
=+
⎛
⎝
⎜
⎞
⎠
⎟
(2)
(3)
(4).
where V
THUVLH
is the desired UV threshold voltage when
V
CC
is rising (L-H), etc.
I
OUT
500mA/DIV
V
OUT
50V/DIV
5ms/DIV
4256 F06
PWRGD
50V/DIV
GATE
50V/DIV
C
L
= 125µF
