LT4256-1/LT4256-2
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Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage Figure 8. Response Time to Overcurrent
Figure 11 shows how the LT4256-1/LT4256-2 are com-
manded to shut off with a logic signal. This is accom-
plished by pulling the gate of the open-drain MOSFET, Q2,
(tied to the UV pin) high.
Short-Circuit Protection
The LT4256-1/LT4256-2 features a programmable foldback
current limit with an electronic circuit breaker that protects
against short circuits or excessive load currents. The
current limit is set by placing a sense resistor (R5)
between V
CC
and SENSE. The current limit threshold is
calculated as:
I
LIMIT
= 55mV/R5 (5)
where R5 is the sense resistor.
To limit excessive power dissipation in the pass transistor
and to reduce voltage spikes on the input supply during
short-circuit conditions at the output, the current folds
back as a function of the output voltage, which is sensed
internally on FB.
If the LT4256-1/LT4256-2 go into current limit when the
voltage on FB is 0V, the current limit circuit drives the
GATE pin to force a constant 14mV drop across the sense
resistor. As the output at FB increases, the voltage across
the sense resistor increases until the FB pin reaches 2V, at
which point the voltage across the sense resistor is held
constant at 55mV (see Figure 7).
For a 0.025 sense resistor, the current limit is set at
2200mA and folds back to 560mA when the output is
shorted to ground. Thus, MOSFET peak power dissipation
under short-circuit conditions is reduced from 105.6W to
26.5W. See the Layout Considerations section for impor-
tant information about board layout to minimize current
limit threshold error.
The LT4256-1/LT4256-2 also features a variable
overcurrent response time. The time required for the part
to regulate the GATE voltage is a function of the voltage
across the sense resistor connected between V
CC
and
SENSE. This helps to eliminate sensitivity to current
spikes and transients that might otherwise unnecessarily
trigger a current limit response and increase MOSFET
dissipation. Figure 8 shows the response time as a func-
tion of the overdrive at SENSE.
TIMER
TIMER provides a method for programming the maximum
time the part is allowed to operate in current limit. When
the current limit circuitry is not active, the TIMER pin is
pulled to GND by a 3µA current source. When the current
limit circuitry becomes active, a 108µA pull-up current
source is connected to TIMER and the voltage will rise with
a slope equal to 105µA/C
TIMER
as long as the circuitry
stays active. Once the desired maximum current limit time
is known, the capacitor value is:
C nF t ms C
A
V
t[] [ ];
.
==
µ
25
105
465
(6)
14mV
0V 2V FB
4256 F07
55mV
V
CC
– V
SENSE
50 100 150 200
4256 F08
12
10
8
6
4
2
RESPONSE TIME (µs)
V
CC
– V
SENSE
(mV)
0
LT4256-1/LT4256-2
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When the TIMER pin reaches 4.65V (typ), the internal fault
latch is set causing GATE to be pulled low and TIMER to be
discharged to GND by the 3µA current source. The part is
not allowed to turn on again until the voltage on TIMER
falls below 0.65V (typ).
TIMER must never be pulled high by a low impedance
because whenever TIMER rises above the upper threshold
(typically 4.65V) the pin characteristics change from a
high impedance current source to a low impedance.
Whenever GATE is commanded off by any fault condition,
it is discharged rapidly, turning off the external MOSFET.
The waveform in Figure 9 shows how the output latches off
following a current fault (LT4256-1). The drop across the
sense resistor is held at 55mV as the timer ramps up. Once
TIMER reaches its shutdown threshold (4.65V typically),
the circuit latches off.
The LT4256-1 latches off after a current limit fault. After
the LT4256-1 latches off, the part may be commanded to
start back up. This is accomplished by cycling UV to
ground and then back high (this command can only be
accepted after TIMER discharges back below the 0.65V
typical threshold, to prevent overheating transistor Q1).
Automatic Restart
The LT4256-2 will automatically restart after an overcurrent
fault. These waveforms are shown in Figure 10.
The LT4256-2 functionality is as follows: When an
overcurrent condition occurs, the GATE pin is servoed to
maintain a constant voltage across the sense resistor, and
the capacitor C2 at the TIMER pin will begin to charge.
When the voltage at the TIMER pin reaches 4.65V (typ),
the GATE pin is pulled low. When the voltage at the TIMER
pin ramps back down to 0.65V (typ), the LT4256-2 turns
on again. If the short-circuit condition at the output still
exists, the cycle will repeat itself indefinitely. The duty
cycle under short-circuit conditions is 3% which prevents
Q1 from overheating.
Figure 9. LT4256-1 Current Limit Waveforms
Figure 10. LT4256-2 Current Limit Waveforms
10ms/DIV
4256 F09
I
OUT
500mA/DIV
V
OUT
50V/DIV
TIMER
5V/DIV
GATE
50V/DIV
I
OUT
500mA/DIV
V
OUT
50V/DIV
TIMER
5V/DIV
GATE
50V/DIV
10ms/DIV
4256 F10
LT4256-1/LT4256-2
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Figure 12. Active Low Enable PWRGD Application
4256 F11
R5
100m
LT4256-1/
LT4256-2
SENSE
6
2
3
4
87
1
5
V
CC
GATE
FB
PWRGD
UV
TIMER
GND
V
IN
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R2
8.06k
R1
64.9k
R7
100
R6
10
V
OUT
V
LOGIC
R4
27k
R8
36.5k
C
L
R10
27k
C2
33nF
C3
0.1µF
C1
10nF
R9
4.02k
Q2
2N3904
PWRGD
GND
D2
SMAT70A
UV = 36V
PWRGD = 40V
Power Good Detection
The LT4256-1/LT4256-2 includes a comparator for moni-
toring the output voltage. The output voltage is sensed
through the FB pin via an external resistor string. The
comparator’s output (PWRGD) is an open collector ca-
pable of operating from a pull-up as high as 80V.
PWRGD can be used to directly enable/disable a power
module with an active high enable input. Figure 12 shows
how to use PWRGD to control an active low enable input
power module. Signal inversion is accomplished by tran-
sistor Q2 and R10.
4256 F07
R5
0.010
LT4256-1/
LT4256-2
SENSE
6
3
4
78
1
5
V
CC
GATE
FB
2
PWRGD
UV
TIMER
GND
V
IN
48V
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R2
8.06k
Q2
VN2222
R1
64.9k
R7
100
R9
4.02k
R6
10
R8
36.5k
V
OUT
48V
4A
R4
51k
C
L
C2
33nF
C3
0.01µF
OFF SIGNAL
FROM MPU
C1
10nF
GND
D2
SMAT70A
UV = 36V
PWRGD = 40V
Figure 11. How to Use a Logic Signal to Control LT4256 Turn-On/-Off
The thresholds for the FB pin are 4.45V (low to high) and
3.99V (high to low). To calculate the PWRGD thresholds,
use the following equations:
R
V
kRR k
V
8=
V
R9, high to low (7)
(8a)
= 4.45V 1+
R8
R9
, low to high (8b)
THPWRGD
THPWRGD
399
1
20 8 9 200
.
Ω≤ + ≤Ω

LT4256-2CS8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Hot Swap Contr. +48V Auto-Retry
Lifecycle:
New from this manufacturer.
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