74ACT125SC Datasheet 74AC125MTC, 74ACT125MTCX, 74AC125SJ | P4-P6

74AC125, 74ACT125 Rev. 1.4.1 4

74AC125, 74ACT125 — Quad Buffer with 3-STATE Outputs

DC Electrical Characteristics for ACT

Notes:

4. All outputs loaded; thresholds on input associated with output under test.

5. Maximum test duration 2.0ms, one output loaded at a time.

6. May be measured per the JEDEC Alternate Method.

Symbol Parameter

V

CC

(V) Conditions

T

A

= +25°C T

A

= –40°C to +85°C

UnitsTyp. Guaranteed Limits

V

IH

Minimum HIGH Level

Input Voltage

4.5 V

OUT

= 0.1V or

V

CC

– 0.1V

1.5 2.0 2.0 V

5.5 1.5 2.0 2.0

V

IL

Maximum LOW Level

Input Voltage

4.5 V

OUT

= 0.1V or

V

CC

– 0.1V

1.5 0.8 0.8 V

5.5 1.5 0.8 0.8

V

OH

Minimum HIGH Level

Output Voltage

4.5 I

OUT

= –50µA 4.49 4.4 4.4 V

5.5 5.49 5.4 5.4

4.5 V

IN

= V

IL

or V

IH

,

I

OH

= –24mA

3.86 3.76

5.5 V

IN

= V

IL

or V

IH

,

I

OH

= –24mA

(4)

4.86 4.76

V

OL

Maximum LOW Level

Output Voltage

4.5 I

OUT

= 50µA 0.001 0.1 0.1 V

5.5 0.001 0.1 0.1

4.5 V

IN

= V

IL

or V

IH

,

I

OL

= 24mA

0.36 0.44

5.5 V

IN

= V

IL

or V

IH

,

I

OL

= 24mA

(4)

0.36 0.44

I

IN

Maximum Input

Leakage Current

5.5 V

I

= V

CC

, GND ±0.1 ±1.0 µA

I

OZ

Maximum 3-STATE

Current

5.5 V

I

= V

IL

, V

IH

;

V

O

= V

CC

, GND

±0.5 ±5.0 µA

I

CCT

Maximum I

CC

/Input 5.5 V

I

= V

CC

– 2.1V

(6)

0.6 1.5 mA

I

OLD

Minimum Dynamic

Output Current

(5)

5.5 V

OLD

= 1.65V Max. 75 mA

I

OHD

5.5 V

OHD

= 3.85V Min. –75 mA

I

CC

Maximum Quiescent

Supply Current

5.5 V

IN

= V

CC

or GND 4.0 40.0 µA

74AC125, 74ACT125 Rev. 1.4.1 5

74AC125, 74ACT125 — Quad Buffer with 3-STATE Outputs

AC Electrical Characteristics for AC

Note:

7. Voltage range 3.3 is 3.3V ± 0.3V. Voltage range 5.0 is 5.0V ± 0.5V.

AC Electrical Characteristics for ACT

Note:

8. Voltage Range 5.0 is 5.0V ± 0.5V.

Capacitance

Symbol Parameter V

CC

(V)

(7)

T

A

= +25°C,

C

L

= 50pF

T

A

= –40°C to +85°C,

C

L

= 50pF

UnitsMin. Typ. Max. Min. Max.

t

PLH

Propagation Delay,

Data to Output

3.3 1.0 6.5 9.0 1.0 10.0 ns

5.0 1.0 5.5 7.0 1.0 7.5

t

PHL

Propagation Delay,

Data to Output

3.3 1.0 6.5 9.0 1.0 10.0 ns

5.0 1.0 5.0 7.0 1.0 7.5

t

PZH

Output Enable Time 3.3 1.0 6.0 10.5 1.0 11.0 ns

5.0 1.0 5.0 7.0 1.0 8.0

t

PZL

Output Enable Time 3.3 1.0 7.5 10.0 1.0 11.0 ns

5.0 1.0 5.5 8.0 1.0 8.5

t

PHZ

Output Disable Time 3.3 1.0 7.5 10.0 1.0 10.5 ns

5.0 1.0 6.5 9.0 1.0 9.5

t

PLZ

Output Disable Time 3.3 1.0 7.5 10.5 1.0 11.5 ns

5.0 1.0 6.5 9.0 1.0 9.5

Symbol Parameter V

CC

(V)

(8)

T

A

= +25°C,

C

L

= 50pF

T

A

= –40°C to +85°C,

C

L

= 50pF

UnitsMin. Typ. Max. Min. Max.

t

PLH

Propagation Delay,

Data to Output

5.0 1.0 6.5 9.0 1.0 10.0 ns

t

PHL

Propagation Delay,

Data to Output

5.0 1.0 7.0 9.0 1.0 10.0 ns

t

PZH

Output Enable Time 5.0 1.0 6.0 8.5 1.0 9.5 ns

t

PZL

Output Enable Time 5.0 1.0 7.0 9.5 1.0 10.5 ns

t

PHZ

Output Disable Time 5.0 1.0 7.0 9.5 1.0 10.5 ns

t

PLZ

Output Disable Time 5.0 1.0 7.5 10.0 1.0 10.5 ns

Symbol Parameter Conditions Typ. Units

C

IN

Input Capacitance V

CC

= OPEN 4.5 pF

C

PD

Power Dissipation Capacitance V

CC

= 5.0V 45.0 pF

74AC125, 74ACT125 Rev. 1.4.1 6

74AC125, 74ACT125 — Quad Buffer with 3-STATE Outputs

Physical Dimensions

Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www

.fairchildsemi.com/packaging/

LAND PATTERN RECOMMENDATION

NOTES: UNLESS OTHERWISE SPECIFIED

A) THIS PACKAGE CONFORMS TO JEDEC

MS-012, VARIATION AB, ISSUE C,

B) ALL DIMENSIONS ARE IN MILLIMETERS.

C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.

D) LANDPATTERN STANDARD:

SOIC127P600X145-14M

E) DRAWING CONFORMS TO ASME Y14.5M-1994

F) DRAWING FILE NAME: M14AREV13

PIN ONE

INDICATOR

8°

0°

SEATING PLANE

DETAIL A

SCALE: 20:1

GAGE PLANE

0.25

X45°

1

0.10

C

BC A

7

M

14

B

A

8

SEE DETAIL A

5.60

0.65

1.70 1.27

8.75

8.50

7.62

6.00

4.00

3.80

(0.33)

1.27

0.51

0.35

1.75 MAX

1.50

1.25

0.25

0.10

0.25

0.19

(1.04)

0.90

0.50

0.36

R0.10

0.50

0.25

74ACT125SC

74ACT125SC

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