DS1236A
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POWER MONITOR
The DS1236A employs a band gap voltage reference and a precision comparator to monitor the 5-volt
supply (V
CC
) in microprocessor-based systems. When an out-of-tolerance condition occurs, the RST and
RST outputs are driven to the active state. The V
CC
trip point (V
CCTP
) is set for 10% operation so that the
RST and RST outputs will become active as V
CC
falls below 4.5 volts (4.37 typical). The V
CCTP
for the
5% operation option (DS1236A-5) is set for 4.75 volts (4.62 typical). The RST and RST signals are
excellent for microprocessor reset control, as processing is stopped at the last possible moment of in-
tolerance V
CC
. On power-up, the RST and RST signals are held active for a minimum of 25 ms (100 ms
typical) after V
CCTP
is reached to allow the power supply and microprocessor to stabilize. Note: The
operation described above is obtained with the reset control pin (RC) connected to GND (NMOS mode).
Please review the reset control section for more information.
WATCHDOG TIMER
The DS1236A provides a watchdog timer function which forces the RST and RST signals to the active
state when the strobe input (ST ) is not stimulated for a predetermined time period. This time period is 400
ms typically with a maximum timeout of 600 ms. The watchdog timeout period begins as soon as RST
and RST are inactive. If a high-to-low transition occurs at the ST input prior to timeout, the watchdog
timer is reset and begins to time out again. The ST input timing is shown in NO TAG. To guarantee the
watchdog timer does not time out, a high-to-low transition on ST must occur at or less than 100 ms
(minimum timeout) from a reset. If the watchdog timer is allowed to time out, the RST and RST outputs
are driven to the active state for 25 ms minimum. The ST input can be derived from microprocessor
address, data, and/or control signals. Under normal operating conditions, these signals would routinely
reset the watchdog timer prior to timeout. If the watchdog timer is not required, two methods have been
provided to disable it.
Permanently grounding the IN pin in the CMOS mode (RC=1) will disable the watchdog. In normal
operation with RC=1, the watchdog is disabled as soon as the IN pin is below V
TP
. With IN grounded, an
NMI output will occur only at power-up, or when the ST pin is strobed. As shown in the NO TAG, a
falling edge on ST will generate an NMI when IN is below V
TP
. This allows the processor to verify that
power is between V
TP
and V
CCTP
, as an NMI will be returned immediately after the ST strobe. The
watchdog timer is not affected by the IN pin when in NMOS mode (RC=0).
If the
NMI signal is required to monitor supply voltages, the watchdog may also be disabled by leaving
the ST input open. Independent of the state of the RC pin, the watchdog is also disabled as soon as V
CC
falls to V
CCTP
.
PUSHBUTTON RESET
An input pin is provided on the DS1236A for direct connection to a pushbutton. The pushbutton reset
input requires an active low signal. Internally, this input is pulled high by a 10k resistor whenever V
CC
is
greater than V
BAT
. The PBRST pin is also debounced and timed such that the RST and RST outputs are
driven to the active state for 25 ms minimum. This 25 ms delay begins as the pushbutton is released from
a low level. A typical example of the power monitor, watchdog timer, and pushbutton reset connections
are shown in NO TAG. The
PBRST input is disabled whenever the IN pin voltage level is less than V
TP
and the reset control (RC) is tied high (CMOS mode). The PBRST input is also disabled whenever V
CC
is
below V
BAT
. Timing of the PBRST -generated RST is illustrated in Figure 1.
