xr XRT85L61
REV. 1.0.2 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
4
12
S2 I Mode Select
13
S3 I Mode Select
14
NC *** This pin must be grounded for normal operation
15
DATMUT I Data Muting:
Connect this pin “High” to mute data output to “Low” state at RPOS/
RNEG. The RLOS pin can be connected to this pin to mute the output
when RLOS occurs.
NOTE: Internally Pulled down with 50 kΩ resistor
16
RNEG O Receive Negative Data Output:
The data is half clock cycle wide.
17
RPOS O Receive Positive Data Output:
The data is half clock cycle wide
18
RCLK O Receive Clock Output
Outputs either 1.544 MHz or 2.048 MHz or 64 kHz clock
19
DGND *** Digital Supply Ground
20
DVDD *** Digital Supply Voltage (3.3V ± 5%)
21
RLOS O Receive Loss of Signal Output
22
400Hz O 400 Hz Clock output for 64 kHz Operation
23
8 kHz O 8 kHz clock output for 64 kHz Operation
24
400Hz_LCV O Line Code Violation for 400 Hz
This pin will stay “High” when 400 Hz is not in sync.
25
8 kHz_LCV/
BPV
O Line Code Violation for 8 kHz in 64 kHz operation
Bipolar Violation:
In E1RZ or T1 mode, every Bipolar violation valid or not valid is indicated
at this pin.
This pin will stay “High” when 8 kHz is not in sync.
26
RCLK_LCV/AIS O Receive Clock Violation.
In 64 kbps operation, every missing pulse will cause this pin to go “High”
for half the clock cycle
AIS Indication
In E1RZ or T1 mode, this output serves as an AIS indicator. AIS will stay
“High” for 250 µs in E1 RZ mode, and in T1 mode, AIS will stay “High” for
3 ms.
27
DATA_INV I Data Invert:
Connect this pin “High” to output active “Low” data at RPOS/RNEG.
NOTE: Internally Pulled down with 50 kΩ resistor
28
RCLK_INV I Receive Clock Invert:
Connect this pin “High” to align the data to change at the falling edge of
RCLK.
NOTE: Internally Pulled down with 50 kΩ resistor
PIN DESCRIPTIONS
PIN #SYMBOL TYPE DESCRIPTION
