NCV8772
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13
APPLICATIONS INFORMATION
The NCV8772 regulator is selfprotected with internal
thermal shutdown and internal current limit. Typical
characteristics are shown in Figure 4 to Figure 33.
Input Decoupling (C
in
)
A ceramic or tantalum 0.1 mF capacitor is recommended
and should be connected close to the NCV8772 package.
Higher capacitance and lower ESR will improve the overall
line and load transient response.
If extremely fast input voltage transients are expected then
appropriate input filter must be used in order to decrease
rising and/or falling edges below 50 V/ms for proper
operation. The filter can be composed of several capacitors
in parallel.
Output Decoupling (C
out
)
The NCV8772 is a stable component and does not require
a minimum Equivalent Series Resistance (ESR) for the
output capacitor. Stability region of ESR vs Output Current
is shown in Figure 17. The minimum output decoupling
value is 1 mF and can be augmented to fulfill stringent load
transient requirements. The regulator works with ceramic
chip capacitors as well as tantalum devices. Larger values
improve noise rejection and load regulation transient
response.
Enable Operation
The Enable pin will turn the regulator on or off. The
threshold limits are covered in the electrical characteristics
table in this datasheet.
Reset Operation
A reset signal is provided on the Reset Output (RO) pin to
provide feedback to the microprocessor of an out of
regulation condition. The timing diagram of reset function
is shown in Figure 33. This is in the form of a logic signal on
RO. Output voltage conditions below the RESET threshold
cause RO to go low. The RO integrity is maintained down
to V
out
= 1.0 V. For 5 V voltage option, the Reset Output
(RO) circuitry includes internal pullup (30 kW) connected
to the output (V
out
) No external pullup is necessary.
RESET DELAY AND RESET THRESHOLD OPTIONS
(DPAK5 AND D2PAK5)
Reset Delay Time Reset Threshold
NCV87721DT
NCV87721D5S
8 ms 93%
NCV87722DT
NCV87722D5S
16 ms 93%
NCV87723DT
NCV87723D5S
32 ms 93%
NCV87724DT
NCV87724D5S
64 ms 93%
NCV87725DT
NCV87725D5S
128 ms 93%
NCV8772ADT
NCV8772AD5S
8 ms 90%
NCV8772BDT
NCV8772BD5S
16 ms 90%
NCV8772CDT
NCV8772CD5S
32 ms 90%
NCV8772DDT
NCV8772DD5S
64 ms 90%
NCV8772EDT
NCV8772ED5S
128 ms 90%
NOTE: The timing values can be selected from the following list:
8, 16, 32, 64, 128 ms. Contact factory for options not
included in ORDERING INFORMATION table on page 14.
Reset Delay Time Select (D2PAK7 only)
Selection of the NCV8772yD7S devices and the state of
the DT pin determines the available Reset Delay times. The
part is designed for use with DT tied to ground or V
out
, but
may be controlled by any logic signal which provides a
threshold between 0.8 V and 2 V. The default condition for
an open DT pin is the slower Reset time (DT = GND
condition). Times are in pairs and are highlighted in the chart
below. Consult factory for availability. The Delay Time
select (DT) pin is logic level controlled and provides Reset
Delay time per the chart. Note the DT pin is sampled only
when RO is low, and changes to the DT pin when RO is high
will not effect the reset delay time.
NCV8772
http://onsemi.com
14
RESET DELAY AND RESET THRESHOLD OPTIONS
(D2PAK7)
DT = GND
Reset
Time
DT = V
out
Reset
Time
Reset
Threshold
NCV87721D7S 8 ms 128 ms 93%
NCV87722D7S 8 ms 32 ms 93%
NCV87723D7S 16 ms 64 ms 93%
NCV87724D7S 32 ms 128 ms 93%
NCV87725D7S 4 ms 8 ms 93%
NCV8772AD7S 8 ms 128 ms 90%
NCV8772BD7S 8 ms 32 ms 90%
NCV8772CD7S 16 ms 64 ms 90%
NCV8772DD7S 32 ms 128 ms 90%
NCV8772ED7S 4 ms 8 ms 90%
NOTE: The timing values can be selected from the following list:
4, 8, 16, 32, 64, 128 ms. Contact factory for options not
included in ORDERING INFORMATION table on page 14.
Thermal Considerations
As power in the NCV8772 increases, it might become
necessary to provide some thermal relief. The maximum
power dissipation supported by the device is dependent
upon board design and layout. Mounting pad configuration
on the PCB, the board material, and the ambient temperature
affect the rate of junction temperature rise for the part. When
the NCV8772 has good thermal conductivity through the
PCB, the junction temperature will be relatively low with
high power applications. The maximum dissipation the
NCV8772 can handle is given by:
P
D
(
max
)
+
ƪ
T
J(max)
* T
A
ƫ
R
qJA
(eq. 1)
Since T
J
is not recommended to exceed 150°C, then the
NCV8772 soldered on 645 mm
2
, 1 oz copper area, FR4 can
dissipate up to 2.35 W (for D2PAK5) when the ambient
temperature (T
A
) is 25°C. See Figure 34 for R
q
JA
versus
PCB area. The power dissipated by the NCV8772 can be
calculated from the following equations:
P
D
+ V
in
ǒ
I
q
@I
out
Ǔ
) I
out
ǒ
V
in
* V
out
Ǔ
(eq. 2)
or
V
in(max)
+
P
D(max)
)
ǒ
V
out
I
out
Ǔ
I
out
) I
q
(eq. 3)
NOTE: Items containing I
q
can be neglected if I
out
>> I
q
.
Figure 34. Thermal Resistance vs. PCB Copper Area
(D2PAK5)
40
50
60
70
80
90
100
0 100 200 300 400 500 600 700
COPPER HEAT SPREADER (mm
2
)
R
q
JA
, THERMAL RESISTANCE (°C/W)
PCB 1 oz Cu
PCB 2 oz Cu
Hints
V
in
and GND printed circuit board traces should be as
wide as possible. When the impedance of these traces is
high, there is a chance to pick up noise or cause the regulator
to malfunction. Place external components, especially the
output capacitor, as close as possible to the NCV8772 and
make traces as short as possible.
ORDERING INFORMATION
Device Output Voltage
Reset Delay Time
(DT = GND/V
out
for D2PAK7)
Reset Threshold Marking Package Shipping
NCV87722DT50RKG 5.0 V 16 ms 93% 772250G DPAK5
(PbFree)
2500 /
Tape & Reel
NCV87721D5S50R4G 5.0 V 8 ms 93% NC
V8772150
D2PAK5
(PbFree)
800 /
Tape & Reel
NCV87725D7S50R4G 5.0 V 4/8 ms 93% NC
V8772550
D2PAK7
(PbFree)
750 /
Tape & Reel
NCV87722DT33RKG 3.3 V 16 ms 93% 772233G DPAK5
(PbFree)
2500 /
Tape & Reel
NCV87722D5S33R4G 3.3 V 16 ms 93% NC
V8772233
D2PAK5
(PbFree)
800 /
Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCV8772
http://onsemi.com
15
PACKAGE DIMENSIONS
DPAK 5, CENTER LEAD CROP
CASE 175AA
ISSUE A
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
D
A
K
B
R
V
S
F
L
G
5 PL
M
0.13 (0.005) T
E
C
U
J
H
T
SEATING
PLANE
Z
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A 0.235 0.245 5.97 6.22
B 0.250 0.265 6.35 6.73
C 0.086 0.094 2.19 2.38
D 0.020 0.028 0.51 0.71
E 0.018 0.023 0.46 0.58
F 0.024 0.032 0.61 0.81
G 0.180 BSC 4.56 BSC
H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
L 0.045 BSC 1.14 BSC
R 0.170 0.190 4.32 4.83
S 0.025 0.040 0.63 1.01
U 0.020 −−− 0.51 −−−
V 0.035 0.050 0.89 1.27
Z 0.155 0.170 3.93 4.32
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
R1 0.185 0.210 4.70 5.33
R1
1234 5
6.4
0.252
0.8
0.031
10.6
0.417
5.8
0.228
SCALE 4:1
ǒ
mm
inches
Ǔ
0.34
0.013
5.36
0.217
2.2
0.086
SOLDERING FOOTPRINT*

NCV87722DT33RKG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
LDO Voltage Regulators 3.3V / 350MA LDO
Lifecycle:
New from this manufacturer.
Delivery:
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