Features
Single 2.7V to 3.6V Supply
Hardware and Software Data Protection
Low Power Dissipation
15 mA Active Current
–20 µA CMOS Standby Current
Fast Read Access Time – 200 ns
Automatic Page Write Operation
Internal Address and Data Latches for 64 Bytes
Internal Control Timer
Fast Write Cycle Times
Page Write Cycle Time: 10 ms Maximum
1 to 64 Byte Page Write Operation
DATA Polling for End of Write Detection
High-reliability CMOS Technology
Endurance: 100,000 Cycles
Data Retention: 10 Years
JEDEC Approved Byte-wide Pinout
Commercial and Industrial Temperature Ranges
Green (Pb/Halide-free) Packaging Option
1. Description
The AT28BV64B is a high-performance electrically erasable programmable read only-
memory (EEPROM). Its 64K of memory is organized as 8,192 words by 8 bits. Manu-
factured with Atmel’s advanced nonvolatile CMOS technology, the device offers
access times to 200 ns with power dissipation of just 54 mW. When the device is
deselected, the CMOS standby current is less than 20 µA.
The AT28BV64B is accessed like a static RAM for the read or write cycle without the
need for external components. The device contains a 64 byte page register to allow
writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to
64 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA
polling of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s AT28BV64B has additional features to ensure high quality and manufactura-
bility. A software data protection mechanism guards against inadvertent writes. The
device also includes an extra 64 bytes of EEPROM for device identification or
tracking.
64K (8K x 8)
Battery-Voltage
Parallel
EEPROM
with Page Write
and Software
Data Protection
AT28BV64B
0299G–PEEPR–04/05
2
0299G–PEEPR–04/05
AT28BV64B
2.1 28-lead PDIP/SOIC Top View
2.2 32-lead PLCC Top View
Note: PLCC package pins 1 and 17 are Don’t Connect.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
4
3
2
1
32
31
30
14
15
16
17
18
19
20
I/O1
I/O2
GND
DC
I/O3
I/O4
I/O5
A7
A12
NC
DC
VCC
WE
NC
2.3 28-lead TSOP Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
A11
A9
A8
NC
WE
VCC
NC
A12
A7
A6
A5
A4
A3
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
2. Pin Configurations
Pin Name Function
A0 - A12 Addresses
CE
Chip Enable
OE Output Enable
WE
Write Enable
I/O0 - I/O7 Data Inputs/Outputs
NC No Connect
DC Don’t Connect
3
0299G–PEEPR–04/05
AT28BV64B
3. Block Diagram
4. Device Operation
4.1 Read
The AT28BV64B is accessed like a static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE
or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their systems.
4.2 Byte Write
A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a
write cycle. The address is latched on the falling edge of CE
or WE, whichever occurs last.
The data is latched by the first rising edge of CE
or WE. Once a byte write has been started, it
will automatically time itself to completion. Once a programming operation has been initiated
and for the duration of t
WC
, a read operation will effectively be a polling operation.
4.3 Page Write
The page write operation of the AT28BV64B allows 1 to 64 bytes of data to be written into the
device during a single internal programming period. A page write operation is initiated in the
same manner as a byte write; the first byte written can then be followed by 1 to 63 additional
bytes. Each successive byte must be written within 100 µs (t
BLC
) of the previous byte. If the
t
BLC
limit is exceeded, the AT28BV64B will cease accepting data and commence the internal
programming operation. All bytes during a page write operation must reside on the same page
as defined by the state of the A6 to A12 inputs. For each WE
high to low transition during the
page write operation, A6 to A12 must be the same.
The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be
loaded in any order and may be altered within the same load period. Only bytes which are
specified for writing will be written; unnecessary cycling of other bytes within the page does
not occur.

AT28BV64B-25SC

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
EEPROM 200NS IND TEMP PKG- 250NS COM TEMP
Lifecycle:
New from this manufacturer.
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