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82V3910AUG

P1-P3P4-P6P7-P9P10-P12P13-P13
IDT82V3910 SHORT FORM DATASHEET SYNCHRONOUS ETHERNET SETS FOR 10GBE AND 40GBE
Pin Assignment 4 July 1, 2013
1 PIN ASSIGNMENT
Figure 2. Pin Assignment (Top View)
IDT Confide
n
tial
1234567891011121314
A
IC1 0 VDDA XTAL1_IN CAP1
IN_APLL1_N
EG
OUT8_NEG IN1 TDI IC7 FF_SRCSW OSCI TMS IC6 TRST
A
B
IC11 VSSA XTAL1_OUT VSSAO
IN_APL L1 _P
OS
OUT8_POS IN2
TDO/
T0_LOS_lNT
VSSAO TCK VSSA VSSA VSSDO VDDDO
B
C
IC4 VDDA NC CAP2
MFRSYNC_2
K_1PPS
FRSYNC_8K_
1PPS
VDDDO VSSDO VDDA VSSA VDDA VDDA INT_REQ OUT9
C
D
VSSA VSSAO CAP3 VSSA VDDA MS/SL VSSD V DDD IC 2 VDDA VSSA VDDA OUT4 OUT5
D
E
XTAL3_IN XTAL3_OUT VSSA VSSAO VSSA SON E T/SDH VSSD VDDD IC1 VSSA VDDA VSSA OUT 2 OUT 3
E
F
VDDD VSSD VSSAO VSSA VDDA VSSAO VSSD VDDD VSSD VDDD EX_SYNC1 V DDDO OUT1 VSSDO
F
G
VSSD VDDD VSSAO VSSAO VSSAO VSSD VDDD IC3 VDDD VSSD EX_SYNC2 IN1 2 IN11 IN13
G
H
VDDAO VSSAO VDDAO VSSAO VSSAO VSSAO VSSD VDDD VSSD VDDD IN10 IN14 RST IN3
H
J
OUT6_NEG OUT6_POS VDDAO VSSAO VDDAO VSSAO VDDAO VSSAO VSSA VDDA T0_LOCK IN9 IN4 IN7
J
K
VSSAO VSSAO VSSAO V DDAO VSSAO VDDAO VSSAO VSSD VDDD VSSAO T4_ LOCK IN8 I2C_SCL I2C_ SDA
K
L
OUT7_NEG OUT7_POS VDDAO VSSAO VSSAO VSSAO VSSAO I2C_AD1 I2C_AD2 CAP4 VSSA CAP5 VSSA CAP6
L
M
VDDAO VSSAO VSSAO VSSAO VDDAO VSSAO VDDAO VSSAO VSSAO VSSAO VSSAO NC XT AL4_OUT XTAL4_IN
M
N
VSSAO OUT 10_POS VSSAO OUT 11_POS VSSAO
IN_APL L2 _P
OS
IN5_POS IN6_POS VSSA XTAL2_OUT VSSA IC9 VSSAO VSSA
N
P
VDDAO OUT 10_NEG VSSAO OUT 11_NE G VDDAO
IN_APLL2_N
EG
IN5_NEG IN6_NEG VDDA XTAL2_ IN V DDA IC8 IC5 VDDA
P
1234567891011121314
Diff
Outp uts
Outputs Inputs Power Ground
Key:
IDT82V3910 SHORT FORM DATASHEET SYNCHRONOUS ETHERNET SETS FOR 10GBE AND 40GBE
Pin Description 5 July 1, 2013
2 PIN DESCRIPTION
Table 1: Pin Description
Name Pin No. I/O Type
Description
1
Global Control Signal
OSCI A11 I CMOS
OSCI: Crystal Oscillator Master Clock
A nominal 12.8000 MHz clock provided by a crystal oscillator is input on this pin. It is the
master clock for the device.
FF_SRCSW A10 I pull-down CMOS
FF_SRCSW: External Fast Selection Enable
During reset, this pin determines the default value of the EXT_SW bit (b4,
MON_SW_HS_CNFG). The EXT_SW bit determines whether the External Fast Selection is
enabled.
High: The default value of the EXT_SW bit (b4, MON_SW_HS_CNFG) is ‘1’ (External Fast
selection is enabled);
Low: The default value of the EXT_SW bit (b4, MON_SW_HS_CNFG) is ‘0’ (External Fast
selection is disabled).
After reset, this pin selects an input clock pair for the T0 DPLL if the External Fast selection
is enabled:
High: Pair IN3 / IN5 is selected.
Low: Pair IN4 / IN6 is selected.
After reset, the input on this pin takes no effect if the External Fast selection is disabled.
MS/SL D6 I pull-up CMOS
MS/SL: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit (b0, MS_SL_CTRL_CNFG), controls whether
the device is configured as the Master or as the Slave. Refer to Chapter 3.14 Master / Slave
Configuration for details.
The signal level on this pin is reflected by the MASTER_SLAVE bit (b1, INPUT_-
MODE_CNFG).
High: The value of the MASTER_SLAVE bit is ‘1’
Low: The value of the MASTER_SLAVE bit is ‘0’
SONET/SDH E6 I pull-down CMOS
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, INPUT_-
MODE_CNFG):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, the value on this pin takes no effect.
RST H13 I pull-up CMOS
RST: Reset
A low pulse of at least 50 µs on this pin resets the device. After this pin is high, the device
will still be held in reset state for 500 ms (typical).
Frame Synchronization Input Signal
EX_SYNC1 F11 I pull-down CMOS
EX_SYNC1: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
EX_SYNC2 G11 I pull-down CMOS
EX_SYNC2: External Sync Input 1
A 2 kHz, 4 kHz, 8 kHz, or 1PPS signal is input on this pin.
Input Clock
IN1 A7 I AMI
IN1: Input Clock 1
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
IN2 B7 I AMI
IN2: Input Clock 2
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
IN3 H14 I pull-down CMOS
IN3: Input Clock 3
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz or 156.25 MHz clock is input on this pin.
IDT82V3910 SHORT FORM DATASHEET SYNCHRONOUS ETHERNET SETS FOR 10GBE AND 40GBE
Pin Description 6 July 1, 2013
IN4 J13 I pull-down CMOS
IN4: Input Clock 4
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz or 156.25 MHz clock is input on this pin.
IN5_POS
IN5_NEG
N7
P7
I LVPECL/LVDS
IN5_POS / IN5_NEG: Positive / Negative Input Clock 5
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
155.52 MHz, 156.25 MHz, 311.04 MHz, 312.5 MHz, 622.08 MHz or 625 MHz clock is differ-
entially input on this pair of pins. Whether the clock signal is LVPECL or LVDS is automati-
cally detected.
Single-ended input for differential input is also supported. Refer to Chapter 7.3.3.5 Single-
Ended Input for Differential Input.
IN6_POS
IN6_NEG
N8
P8
I LVPECL/LVDS
IN6_POS / IN6_NEG: Positive / Negative Input Clock 6
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
155.52 MHz, 156.25 MHz, 311.04 MHz or 312.5 MHz, 622.08 MHz or 625 MHz clock is dif-
ferentially input on this pair of pins. Whether the clock signal is LVPECL or LVDS is automat-
ically detected.
Single-ended input for differential input is also supported. Refer to Chapter 7.3.3.5 Single-
Ended Input for Differential Input.
IN7 J14 I pull-down CMOS
IN7: Input Clock 7
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz or 156.25 MHz clock is input on this pin.
IN8 K12 I pull-down CMOS
IN8: Input Clock 8
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
125MHz, 155.52 MHz or 156.25 MHz clock is input on this pin.
IN9 J12 I pull-down CMOS
IN9: Input Clock 9
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
155.52 MHz or 156.25 MHz clock is input on this pin.
IN10 H11 I pull-down CMOS
IN10: Input Clock 10
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
155.52 MHz or 156.25 MHz clock is input on this pin.
IN11 G13 I pull-down CMOS
IN11: Input Clock 11
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
155.52 MHz or 156.25 MHz clock is input on this pin.
In Slave operation, the frequency of the T0 selected input clock IN11 is recommended to be
6.48 MHz.
IN12 G12 I pull-down CMOS
IN12: Input Clock 12
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
155.52 MHz or 156.25 MHz clock is input on this pin.
IN13 G14 I pull-down CMOS
IN13: Input Clock 13
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
155.52 MHz or 156.25 MHz clock is input on this pin.
Table 1: Pin Description (Continued)
Name Pin No. I/O Type
Description
1
P1-P3P4-P6P7-P9P10-P12P13-P13

82V3910AUG

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Buy 82V3910AUG
Manufacturer:
IDT
Description:
Clock Generators & Support Products SyncE SETS for 10 GbE and 40GbE
Lifecycle:
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