IDT82V3910 SHORT FORM DATASHEET SYNCHRONOUS ETHERNET SETS FOR 10GBE AND 40GBE
Pin Description 7 July 1, 2013
IN14 H12 I pull-down CMOS
IN14: Input Clock 14
A 1 PPS, 2 kHz, 4 kHz, N x 8 kHz
3
, 1.544 MHz (SONET) / 2.048 MHz (SDH), 6.25 MHz,
6.48 MHz, 10MHz, 19.44 MHz, 25MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz,
155.52 MHz or 156.25 MHz clock is input on this pin.
IN_APLL1_POS
IN_APLL1_NEG
B5
A5
I pull-down
I pull-up/
pull-down
LVPECL/LVDS/
LVHSTL/SSTL/
HCSL
IN_APLL1_POS / IN_APLL1_NEG: Input Clock to APLL1
Direct input clock to APLL1. This pin is used for test. It can be left floating or a 1kΩ resistor
can be tied from IN_APLL1_POS to ground.
IN_APLL2_POS
IN_APLL2_NEG
N6
P6
I pull-down
I pull-up/
pull-down
LVPECL/LVDS/
LVHSTL/SSTL/
HCSL
IN_APLL2_POS / IN_APLL2_NEG: Input Clock APLL2
Direct input clock to APLL2. This pin is used for test. It can be left floating or a 1kΩ resistor
can be tied from IN_APLL2_POS to ground.
Output Frame Synchronization Signal
FRSYN-
C_8K_1PPS
C6 O CMOS
FRSYNC_8K_1PPS: 8 kHz Frame Sync Output
An 8 kHz signal or a 1PPS Frame Pulse is output on this pin.
MFRSYN-
C_2K_1PPS
C5 O CMOS
MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output
A 2 kHz signal or a 1PPS Frame Pulse is output on this pin.
Output Clock
OUT1
OUT2
OUT3
OUT4
OUT5
F13
E13
E14
D13
D14
OCMOS
OUT1 ~ OUT5: Output Clock 1 ~ 5
A 1 pps, 400 Hz, 2 kHz, 8 kHz, 64 kHz, N x E1
4
, N x T1
5
, N x 13.0 MHz
6
, N x 3.84 MHz
7
,
5 MHz, 10 MHz, 20 MHz, E3, T3, 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz,
77.76 MHz, 25MHz, or 125 MHz clock is output on these pins.
OUT6_POS
OUT6_NEG
J2
J1
O LVPECL/LVDS
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
A SONET based (77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz), Ethernet based (25
MHz, 125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz), or Ethernet LAN based (161.1328125
MHz, 322.265625 MHz, 644.53125 MHz) clock is differentially output on this pair of pins from
APLL1.
OUT7_POS
OUT7_NEG
L2
L1
O LVPECL/LVDS
OUT7_POS / OUT7_NEG: Positive / Negative Output Clock 7
A SONET based (77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz), Ethernet based (25
MHz, 125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz), or Ethernet LAN based (161.1328125
MHz, 322.265625 MHz, 644.53125 MHz) clock is differentially output on this pair of pins from
APLL1.
OUT8_POS
OUT8_NEG
B6
A6
OAMI
OUT8_POS / OUT8_NEG: Positive / Negative Output Clock 8
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is differentially output on this
pair of pins.
OUT9 C14 O CMOS
OUT9: Output Clock 9
A 1.544 MHz (SONET) / 2.048 MHz (SDH) BITS/SSU clock is output on this pin.
OUT10_POS
OUT10_NEG
N2
P2
O LVPECL/LVDS
OUT10_POS / OUT10_NEG: Positive / Negative Output Clock 10
A SONET based (77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz), Ethernet based (25
MHz, 125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz), or Ethernet LAN based (161.1328125
MHz, 322.265625 MHz, 644.53125 MHz) clock is differentially output on this pair of pins from
APLL2.
OUT11_POS
OUT11_NEG
N4
P4
O LVPECL/LVDS
OUT11_POS / OUT11_NEG: Positive / Negative Output Clock 11
A SONET based (77.76 MHz, 155.52 MHz, 311.04 MHz, 622.08 MHz), Ethernet based (25
MHz, 125 MHz, 156.25 MHz, 312.5 MHz, 625 MHz), or Ethernet LAN based (161.1328125
MHz, 322.265625 MHz, 644.53125 MHz) clock is differentially output on this pair of pins from
APLL2.
Miscellaneous
CAP1, CAP2,
CAP3
A4, C4, D3 O Analog
CAP1, CAP2 and CAP3: Analog Power Filter Capacitor connection 1 to 3
Connect a 10uF capacitor in parallel with a low ESR 100nF capacitor between these pins
and VSS1
Table 1: Pin Description (Continued)
Name Pin No. I/O Type
Description
1
