AMIS−492x0
www.onsemi.com
11
Tri-level Modulator
The tri-level modulator switches current signals into a
summing node. The slew rate controller converts the current
to a voltage signal, VDRV. The DC level of silence (V
S
) is
nominally 2.5 V. Transmission high (V
H
) is nominally 2.9 V
and transmission low (V
L
) is nominally 2.1 V, yielding an
amplitude of 0.8 V.
Figure 7. Tri-level Modulator
19
21
VDRV
CRT
1.2 kW
A3
+
−
VCC
VMID
N_VL
N_Vs
80 kW
4R
1.2 kW
1.2 kW
80 kW
4R
20 kW
R
Active Low
Active Low
20R
400 kW
Tri-level Modulator & Slew Control
Slew Rate Controller
Amplifier (A3), shown in the above figure, controls the
slew rate. The amplifier converts the current signals from the
tri-level modulator to a voltage signal, VDRV. It controls its
slew rate with a capacitor (C
RT
) connected to the CRT pin.
The waveform at the VDRV pin is symmetric and the
fall/rise times are determined by the following equation:
t
F
,t
R
+ 2.0[ms] ) 0.12[msńpF] C
RT
(eq. 3)
The constant part comes from the internal capacitor (not
shown). It is recommended to make a guard pattern on your
circuit board around the CRT pin and the hot side of C
RT
to
avoid unnecessary interference.
Current Drive Amplifier
The drive amplifier is an operational amplifier optimized
to drive current drivers for 31.25 kbps voltage-mode
medium. Its input and output signals are exposed to allow
flexible design of the external driver. Note that this amplifier
cannot directly sink the necessary current from the medium.
In the following drive circuit the current (I
BUS
) through the
current-detect resister (R
F
) is determined by the following
equation.
I
bus
+
ƪ
R
3
V
mid
ǒ
R
12
) R
11
Ǔ
ƫ
*
ƪ
V
DRV
ǒ
R
2
R
11
) R
3
R
11
Ǔ
ƫ
*
ƪ
R
F
ǒ
R
2
R
12
) R
3
R
12
Ǔ
ƫ
(eq. 4)
A diode and/or a resistor connected to the emitter are
necessary to shift the DC level of CCOUT and to suppress
the loop gain. The resistance value depends on your design
(overall gain and emitter current).
Figure 8. Current Control Circuit
25
R
3
24
23
R
2
R
11
R
12
R
f
Bus
A4
+
−
VCC
CCOUT
CCINP
CCINM
VDRVVmid
Receive Block
The receive block contains three sub-blocks, which are
internally connected:
1. A Band Pass Filter – to filter the desired incoming
communication signal.
2. Carrier Detector – generates the RxA signal by
detecting the signal amplitude.
3. Zero-cross Detector generates the RxS signal by
detecting the high/low transitions of the
Manchester code.
Band Pass Filter
The band pass filter is a series connection of a high-pass
and a low-pass filters each having two poles. Each filter is
comprised of a voltage follower and on chip resisters, so
only four external capacitors are necessary. The following
figure shows an internal circuit and the connection of
external capacitors. Cut-off frequency, f
L
, of the high-pass
