MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________
13
AVDD SUPPLY CURRENT
vs. ADC SAMPLING RATE
MAXQ7670 toc28
ADC SAMPLING RATE (ksps)
AVDD SUPPLY CURRENT (mA)
10 100
5.5
5.6
5.7
5.4
1 1000
PGA GAIN = 16V/V
DVDDIO DYNAMIC SUPPLY CURRENT
vs. DVDDIO SUPPLY VOLTAGE
MAXQ7670 toc29
DVDDIO SUPPLY VOLTAGE (V)
DVDDIO SUPPLY CURRENT (µA)
2.6252.5002.375
120
140
160
180
200
220
240
260
100
2.250 2.750
NOTE 6 IN
EC CHARACTERISTICS
DVDDIO DYNAMIC SUPPLY CURRENT
vs. TEMPERATURE
MAXQ7670 toc30
TEMPERATURE (°C)
DVDDIO SUPPLY CURRENT (µA)
1109580655035205-10-25
210
220
230
240
250
200
-40 125
NOTE 6 IN
EC CHARACTERISTICS
DVDDIO STATIC SUPPLY CURRENT
vs. DVDDIO SUPPLY VOLTAGE
MAXQ7670 toc31
DVDDIO SUPPLY VOLTAGE (V)
DVDDIO SUPPLY CURRENT (µA)
5.1255.004.875
60
80
100
120
140
160
40
4.750 5.250
DVDDIO STATIC SUPPLY CURRENT
vs. TEMPERATURE
MAXQ7670 toc32
TEMPERATURE (°C)
DVDDIO SUPPLY CURRENT (µA)
1109580655035205-10-25
60
80
100
120
140
160
40
-40 125
Typical Operating Characteristics (continued)
(V
DVDDIO
= 5.0V, V
AVDD
= 3.3V, V
DVDD
= 2.5V, f
SYSCLK
= 16MHz, ADC resolution = 10 bits, V
REFDAC
= 3.3V, T
A
= +25°C, unless
otherwise noted.)
DVDDIO INCREMENTAL SUPPLY CURRENT
vs. DVDDIO SUPPLY VOLTAGE
MAXQ7670 toc33
DVDDIO SUPPLY VOLTAGE (V)
DVDDIO SUPPLY CURRENT (µA)
5.1255.0004.875
1
2
3
4
5
0
4.750 5.250
BOI ENABLED
DVDDIO INCREMENTAL SUPPLY CURRENT
vs. TEMPERATURE
MAXQ7670 toc34
TEMPERATURE (°C)
DVDDIO SUPPLY CURRENT (µA)
5-10-25 503520 110958065
1
2
3
4
5
0
-40 125
BOI ENABLED
ADC SAMPLING ERROR
vs. INPUT SOURCE IMPEDANCE
SOURCE IMPEDANCE ()
SAMPLING ERROR (LSB)
MAXQ7670 toc35
-5
-4
-3
-2
-1
0
1
1 10 100 1000 10,000 100,000
PGA GAIN = 16V/V
f
S
= 150.9ksps
SNR
FREQUENCY (kHz)
MAGNITUDE (dB)
MAXQ7670 toc36
0 5 10 15 20 25 30 35
-140
-120
-100
-80
-60
-40
-20
0
f
IN
= 10kHz
f
S
= 62.5ksps
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
14 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 AIN7
Analog Input Channel 7. AIN7 is multiplexed to the PGA or ADC as single-ended analog input 7 or as a
differential input with AIN6. As a differential input, the polarity of AIN7 is negative.
2 AIN6
Analog Input Channel 6. AIN6 is multiplexed to the PGA or ADC as a single-ended analog input 6 or as a
differential input with AIN7. As a differential input, the polarity of AIN6 is positive.
3 AIN5
Analog Input Channel 5. AIN5 is multiplexed to the PGA or ADC as single-ended analog input 5 or as a
differential input with AIN4. As a differential input, the polarity of AIN5 is negative.
4 AIN4
Analog Input Channel 4. AIN4 is multiplexed to the PGA or ADC as single-ended analog input 4 or as a
differential input with AIN5. As a differential input, the polarity of AIN4 is positive.
5 REFADC ADC External Reference Input. Connect an external reference between 1V and V
AVDD
.
6 AGND Analog Ground
7 AIN3
Analog Input Channel 3. AIN3 is multiplexed to the PGA or ADC as single-ended analog input 3 or as a
differential input with AIN2. As a differential input, the polarity of AIN3 is negative.
8 AIN2
Analog Input Channel 2. AIN2 is multiplexed to the PGA or ADC as single-ended analog input 2 or as a
differential input with AIN3. As a differential input, the polarity of AIN2 is positive.
9 AIN1
Analog Input Channel 1. AIN1 is multiplexed to the PGA or ADC as single-ended analog input 1 or as a
differential input with AIN0. As a differential input, the polarity of AIN1 is negative.
10 AIN0
Analog Input Channel 0. AIN0 is multiplexed to the PGA or ADC as single-ended analog input 0 or as a
differential input with AIN1. As a differential input, the polarity of AIN0 is positive.
11 I.C. Internally Connected. Connect to GNDIO for proper operation.
12 P0.0 Port 0 Bit 0. P0.0 is a general-purpose digital I/O with interrupt/wake-up capability.
13 P0.1 Port 0 Bit 1. P0.1 is a general-purpose digital I/O with interrupt/wake-up capability.
14 P0.2 Port 0 Bit 2. P0.2 is a general-purpose digital I/O with interrupt/wake-up capability.
15, 22, 38 GNDIO Digital I/O Ground and Regulator Ground
16 CANRXD CAN Bus Receiver Input. CAN receiver input.
17 CANTXD CAN Bus Transmitter Output. CAN transmitter output.
18 SS
Active-Low, SPI Port Slave Select Input. In SPI slave mode, this is the slave select input. In SPI master
mode, this is an input and connection is optional (connect if mode fault enable is required, refer to the
MAXQ7670 User’s Guide for a description of the SPICN register). In master mode, use an available GPIO
as a slave selector and pull SS high to DVDDIO through a pullup resistor.
19 P0.6/T0
Port 0 Bit 6/Timer 0 I/O. P0.6 is a general-purpose digital I/O with interrupt/wake-up input capability. T0 is a
primary timer/PWM input or output. The alternative function, T0, is selected using the T2CNA0 register.
When this function is selected, it overrides the GPIO functionality.
20 P0.7/T0B
Port 0 Bit 7/Timer 0 Output. P0.7 is a general-purpose digital I/O with interrupt/wake-up input capability.
T0B is a secondary timer/PWM output. The alternative function, T0B, is selected using the T2CNB0 register.
When this function is selected, it overrides the GPIO functionality.
21, 39 DVDDIO
Digital I/O Supply Voltage and Regulator Supply Input. DVDDIO supplies all digital I/O except for XIN and
XOUT, and supplies power to the two internal linear regulators, AVDD and DVDD. Bypass DVDDIO to
GNDIO with a 0.1µF capacitor as close as possible to the device.
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________ 15
Pin Description (continued)
PIN NAME FUNCTION
23 SCLK
SPI Serial Clock. SCLK is the SPI interface serial clock I/O. In SPI master mode, SCLK is an output. While in
SPI slave mode, SCLK is an input.
24 MOSI
SPI Serial Data I/O. MOSI is the SPI interface serial data output in master mode or serial data input in slave
mode.
25 MISO
SPI Serial Data I/O. MISO is the SPI interface serial data input in master mode or serial data output in slave
mode.
26 REGEN2
Active-Low +2.5V Linear Regulator Enable Input. Connect REGEN2 to GNDIO to enable the +2.5V linear
regulator. Connect to DVDDIO to disable the +2.5V linear regulator.
27 TDO JTAG Serial Test Data Output. TDO is the JTAG serial test, data output.
28 TMS JTAG Test Mode Select. TMS is the JTAG test mode, select input.
29 TDI JTAG Serial Test Data Input. TDI is the JTAG serial test, data input.
30 TCK JTAG Serial Test Clock Input. TCK is the JTAG serial test, clock input.
31
P0.4/
ADCCNV
Port 0 Bit 4/ADC Start Conversion Control. P0.4 is a general-purpose digital I/O with interrupt/wake-up
capability. ADCCNV is a firmware-configurable, rising or falling edge, start/convert signal used to trigger
ADC conversions. The alternative function, ADCCNV, is selected using the register bits ACNT[2:0]. When
using ADCCNV as a trigger for ADC conversion, set P0.4/ADCCNV as an input using the PD0 register. This
action prevents any unintentional interference in the SARADC operation.
32 P0.5 Port 0 Bit 5. P0.5 is a general-purpose digital I/O with interrupt/wake-up capability.
33 RESET
Reset Input/Output. Active-low input/output with internal 55k pullup to DVDDIO. Drive low to reset the
MAXQ7670. The MAXQ20 µC core holds RESET low during POR and during DVDD brownout conditions.
34 DGND Digital Ground
35 XOUT
High-Frequency Crystal Output. Connect an external crystal to XIN and XOUT for normal operation, or leave
unconnected if XIN is driven with an external clock source. Leave unconnected if an external clock source
is not used.
36 XIN
H i g h- Fr eq uency C r ystal Inp ut. C onnect an exter nal cr ystal or r esonator to X IN and X OU T for nor m al op er ati on,
or d r i ve X IN w i th an exter nal cl ock sour ce. Leave unconnected i f an exter nal cl ock sour ce i s not used .
37 DVDD
D i g i tal S up p l y V ol tag e. D V D D sup p l i es i nter nal d i g i tal cor e and fl ash m em or y. D V D D i s d i r ectl y connected to
the outp ut of the i nter nal + 2.5V l i near r eg ul ator . D i sab l e the i nter nal r eg ul ator ( thr oug h REG EN 2) to connect an
exter nal sup p l y. Byp ass D V D D to D GN D w i th a 0.1µF cap aci tor as cl ose as p ossi b
l e to the d evi ce.
40 AVDD
Analog Supply Voltage. AVDD supplies PGA and ADC. AVDD is directly connected to the output of the
internal +3.3V linear regulator. Disable the internal regulator (via software) to connect an external supply.
Bypass AVDD to AGND with a 0.1µF capacitor as close as possible to the device.
EP Exposed Pad. Connect EP to the ground plane.

MAXQ7670ATL+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
16-bit Microcontrollers - MCU MCU w/12-Bit ADC PGA 64KB Flash & CAN Int
Lifecycle:
New from this manufacturer.
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