SL3S1003_1013 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 21 May 2015
201237 8 of 43
NXP Semiconductors
SL3S1003_1013
UCODE G2iM and G2iM+
9. Mechanical specification
The SL3S10x3 wafers are offered with 120 mm thickness and 7mm Polyimide spacer.
This robust structure with the enhanced Polyimide spacer supports easy assembly due to
low assembly variations.
9.1 Wafer specification
See Ref. 20 “Data sheet - Delivery type description – General specification for 8” wafer on
UV-tape with electronic fail die marking, BU-ID document number: 1093**”.
9.1.1 Wafer
Table 5. Specifications
Wafer
Designation each wafer is scribed with batch number and
wafer number
Diameter 200 mm (8”)
Thickness 120 m 15 m
Number of pads 4
Pad location non diagonal/ placed in chip corners
Distance pad to pad RFN-RFP 333.0 m
Distance pad to pad OUT-RFN 513.0 m
Process CMOS 0.14 mm
Batch size 25 wafers
Potential good dies per wafer 100544
Wafer backside
Material Si
Treatment ground and stress release
Roughness R
a
max. 0.5 m, R
t
max. 5 m
Chip dimensions
Die size including scribe 0.615 mm 0.475 mm = 0.292 mm
2
Scribe line width: x-dimension = 15 m
y-dimension = 15 m
Passivation on front
Type Sandwich structure
Material PE-Nitride (on top)
Thickness 1.75 m total thickness of passivation
Polyimide spacer 7 m
Au bump
Bump material > 99.9% pure Au
Bump hardness 35 – 80 HV 0.005
Bump shear strength > 70 MPa
Bump height 25 m
[1]
Bump height uniformity
