www.fairchildsemi.com 2
74F182
Unit Loading/Fan Out
Functional Description
The 74F182 carry lookahead generator accepts up to four
pairs of Active LOW Carry Propagate (P
0
–P
3
) and Carry
Generate (G
0
–G
3
) signals and an Active HIGH Carry input
(C
n
) and provides anticipated Active HIGH carries (C
n + x
,
C
n+y
, C
n+z
) across four groups of binary adders. The
74F182 also has Active LOW Carry Propagate (P
) and
Carry Generate (G
) outputs which may be used for further
levels of lookahead. The logic equations provided at the
outputs are:
C
n+x
= G
0
+ P
0
C
n
C
n+y
= G
1
+ P
1
G
0
+ P
1
P
0
C
n
C
n+z
= G
2
+ P
2
G
1
+ P
2
P
1
G
0
+ P
2
P
1
P
0
C
n
G = G
3
+ P
3
G
2
+ P
3
P
2
G
1
+ P
3
P
2
P
1
G
0
P = P
2
P
2
P
1
P
0
Also, the 74F182 can be used with binary ALUs in an
active LOW or active HIGH input operand mode. The con-
nections (Figure 1) to and from the ALU to the carry looka-
head generator are identical in both cases. Carries are
rippled between lookahead blocks. The critical speed path
follows the circled numbers. There are several possible
arrangements for the carry interconnects, but all achieve
about the same speed. A 28-bit ALU is formed by dropping
the last 74F181 or 74F381.
*ALUs may be either 74F181 or 74F381
FIGURE 1. 32-Bit ALU with Rippled Carry between 16-Bit Lookahead ALUs
Pin Names Description
U.L.
Input I
IH
/I
IL
HIGH/LOW
Output I
OH
/I
OL
C
n
Carry Input 1.0/2.0 20 µA/−1.2 mA
G
0
, G
2
Carry Generate Inputs (Active LOW) 1.0/14.0 20 µA/−8.4 mA
G
1
Carry Generate Input (Active LOW) 1.0/16.0 20 µA/−9.6 mA
G
3
Carry Generate Input (Active LOW) 1.0/8.0 20 µA/−4.8 mA
P
0
, P
1
Carry Propagate Inputs (Active LOW) 1.0/8.0 20 µA/−4.8 mA
P
2
Carry Propagate Input (Active LOW) 1.0/6.0 20 µA/−3.6 mA
P
3
Carry Propagate Input (Active LOW) 1.0/4.0 20 µA/−2.4 mA
C
n+x
− C
n+z
Carry Outputs 50/33.3 −1 mA/20 mA
G
Carry Generate Output (Active LOW) 50/33.3 −1 mA/20 mA
P
Carry Propagate Output (Active LOW) 50/33.3 −1 mA/20 mA
