74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 31 December 2012 4 of 23
NXP Semiconductors
74HC4094; 74HCT4094
8-stage shift-and-store bus register
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 5. Pin configuration DIP16 and SO16 Fig 6. Pin configuration SSOP16 and TSSOP16
74HC4094
74HCT4094
STR V
CC
DOE
CP QP4
QP0 QP5
QP1 QP6
QP2 QP7
QP3 QS2
GND QS1
001aan577
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74HC4094
74HCT4094
STR V
CC
DOE
CP QP4
QP0 QP5
QP1 QP6
QP2 QP7
QP3 QS2
GND QS1
001aan578
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
STR 1 strobe input
D 2 data input
CP 3 clock input
QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output
V
SS
8 ground supply voltage
QS1, QS2 9, 10 serial output
OE 15 output enable input
V
DD
16 supply voltage
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 31 December 2012 5 of 23
NXP Semiconductors
74HC4094; 74HCT4094
8-stage shift-and-store bus register
7. Functional description
[1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs.
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= positive-going transition; = negative-going transition;
Z = HIGH-impedance OFF-state; NC = no change;
Q6S = the data in register stage 6 before the LOW to HIGH clock transition;
Q7S = the data in register stage 7 before the HIGH to LOW clock transition.
Table 3. Function table
[1]
Inputs Parallel outputs Serial outputs
CP OE STR D QP0 QPn QS1 QS2
LXXZZQ6SNC
LXXZZNCQ7S
HLXNCNCQ6SNC
HHLLQPn 1Q6S NC
HHHHQPn 1Q6S NC
H H H NCNCNCQ7S
Fig 7. Timing diagram
001aaf117
CLOCK INPUT
DATA INPUT
STROBE INPUT
OUTPUT ENABLE INPUT
INTERNAL Q0S (FF 0)
OUTPUT QP0
INTERNAL Q6S (FF 6)
OUTPUT QP6
SERIAL OUTPUT QS1
SERIAL OUTPUT QS2
Z-state
Z-state
74HC_HCT4094 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 31 December 2012 6 of 23
NXP Semiconductors
74HC4094; 74HCT4094
8-stage shift-and-store bus register
8. Limiting values
[1] For DIP16 package: P
tot
derates linearly with 12 mW/K above 70 C.
[2] For SO16: P
tot
derates linearly with 8 mW/K above 70 C.
For SSOP16 and TSSOP16 packages: P
tot
derates linearly with 5.5 mW/K above 60 C.
9. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7 V
I
IK
input clamping current V
I
< 0.5 V or V
I
>V
CC
+0.5 V - 20 mA
I
OK
output clamping current V
O
< 0.5 V or V
O
>V
CC
+0.5V - 20 mA
I
O
output current V
O
= 0.5 V to (V
CC
+0.5V) - 25 mA
I
CC
supply current - +50 mA
I
GND
ground current - 50 mA
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation DIP16 package
[1]
- 750 mW
SO16, SSOP16 and TSSOP16 packages
[2]
- 500 mW
Table 5. Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions 74HC4094 74HCT4094 Unit
Min Typ Max Min Typ Max
V
CC
supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V
V
I
input voltage 0 - V
CC
0- V
CC
V
V
O
output voltage 0 - V
CC
0- V
CC
V
T
amb
ambient temperature 40 +25 +125 40 +25 +125 C
t/V input transition rise and fall rate V
CC
= 2.0 V - - 625 - - - ns/V
V
CC
= 4.5 V - 1.67 139 - 1.67 139 ns/V
V
CC
= 6.0 V--83---ns/V

74HC4094N,652

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC REGISTER BUS 8STAGE 16DIP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet