ZL30722 Product Brief
2
Microsemi Corporation
1. Detailed Features
1.1 Time Synchronization Algorithm
External algorithm controls software digital PLL to adjust frequency and phase alignment
Frequency, phase and time synchronization over IP, MPLS and Ethernet packet networks
Frequency accuracy performance for GSM, WCDMA-FDD, LTE-FDD femtocell, small cell (residential,
urban, rural, enterprise), picocell and macrocell applications, with target performance less than ±15 ppb
Frequency performance for ITU-T G.8263 for PEC-S-F (Packet Equipment Clock - Slave - Frequency)
Frequency performance for ITU-T G.823 and G.824 synchronization interface, as well as G.8261 PNT
EEC, PNT PEC and CES interface specifications
Phase synchronization performance for WCDMA-TDD, Mobile WiMAX, TD-SCDMA, CDMA2000, LTE-
TDD and LTE-A femtocell, small cell (residential, urban, rural, enterprise), picocell and macrocell
applications with target performance less than ± 1µs phase alignment.
hase performance for ITU-T packet clock drafts or recommendations in development
o ITU-T G.8273.2 T-BC & T-TSC, when not using SyncE input
o ITU-T G.8273.4 T-BC-P & T-TSC-P
Supports hybrid mode for mixing SyncE and IEEE1588 inputs
Time Synchronization for TAI, UTC-traceability and GNSS/GPS replacement.
Client reference switching between multiple servers
Client holdover when server packet connectivity is lost
Client synchronization to best server with monitoring of secondary server references
1.2 Input Clock Features
Three input clocks, two differential or single-ended, one single-ended
Input clocks can be any frequency from 8kHz up to 1250MHz (differential) or 300MHz (single-ended)
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, wireless
Inputs constantly monitored by programmable activity monitors and frequency monitors
Fast activity monitor can disqualify the selected reference after a few missing clock cycles
Frequency measurement and monitoring with 1ppm resolution and accept/reject hysteresis
Optional input clock invalidation on GPIO assertion to react to LOS signals from PHYs
1.3 Electrical Clock Engine Features
Very high-resolution DPLL architecture
State machine automatically transitions between tracking and freerun/holdover states
Revertive or nonrevertive reference selection algorithm
Programmable bandwidth from 0.1Hz to 500Hz
Less than 0.1dB gain peaking
Programmable phase-slope limiting
Programmable tracking range (i.e. hold-in range)
Truly hitless reference switching with <200ps output clock phase transient
o Physical-clock-to-physical-clock reference switching
o Physcial-clock-to-packet-timing reference switching
o Packet-timing-to-physcial-clock reference switching
o Packet-timing-to-packet-timing reference switching
Support for SyncE and SONET/SDH equipment clock specifications
o ITU-T G.8262 option 1 EEC
o ITU-T G.8262 option 2
o ITU-T G.813 option 1 SEC
o IUT-T G.813 option 2
Output phase adjustment in 10ps steps
High-resolution frequency and phase measurement
Fast detection of input clock failure and transition to holdover mode
Holdover frequency averaging with programmable averaging time and delay time
