RT8072
13
DS8072-02 August 2014 www.richtek.com
©
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θ
JA
, is layout dependent. For
SOP-8 (Exposed Pad) packages, the thermal resistance,
θ
JA
, is 49°C/W on a standard JEDEC 51-7 four-layer
thermal test board. For WDFN-12L 3x3 packages, the
thermal resistance, θ
JA
, is 60°C/W on a standard JEDEC
51-7 four-layer thermal test board. The maximum power
dissipation at T
A
= 25°C can be calculated by the following
formulas :
P
D(MAX)
= (125°C − 25°C) / (49°C/W) = 2.041W for
SOP-8 (Exposed Pad) package
P
D(MAX)
= (125°C − 25°C) / (60°C/W) = 1.667W for
WDFN-12L 3x3 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance, θ
JA
. The derating curves in Figure 6 allow the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Figure 6. Derating Curve of Maximum Power Dissipation
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of RT8072.
A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small-signal components returning
to the GND pin at one point that is then connected to
the PGND pin close to the IC. The exposed pad should
be connected to GND.
Connect the terminal of the input capacitor(s), C
IN
, as
close as possible to the VIN pin. This capacitor provides
the AC current into the internal power MOSFETs.
LX node is with high frequency voltage swing and should
be kept within small area. Keep all sensitive small-signal
nodes away from the LX node to prevent stray capacitive
noise pick-up.
Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise
of power components.
Connect the FB pin directly to the feedback resistors.
The resistor divider must be connected between V
OUT
and GND.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
0 25 50 75 100 125
Ambient Temperature (°C)
Maximum Power Dissipation (W
WDFN-12L 3x3
Four-Layer PCB
SOP-8 (Exposed Pad)
