LTC2271CUKG#PBF Datasheet LTC2271CUKG#PBF, LTC2271IUKG#PBF, LTC2271CUKG#TRPBF | P16-P18

LTC2271

2271f

Encode Input

The signal quality of the encode inputs strongly affects

the A/D noise performance. The encode inputs should

be treated as analog signals—do not route them next to

digital traces on the circuit board. There are two modes

of operation for the encode inputs: the differential encode

mode (Figure 10), and the single-ended encode mode

(Figure 11).

The differential encode mode is recommended for sinu-

soidal, PECL, or LVDS encode inputs (Figures 12, 13). The

encode inputs are internally biased to 1.2V through 10k

equivalent resistance. The encode inputs can be taken above

(up to 3.6V), and the common mode range is from 1.1V

to 1.6V. In the differential encode mode, ENC

–

should stay

at least 200mV above ground to avoid falsely triggering the

single-ended encode mode. For good jitter performance

ENC

should have fast rise and fall times.

The single-ended encode mode should be used with

CMOS encode inputs. To select this mode, ENC

–

is con-

nected to ground and ENC

is driven with a square wave

APPLICATIONS INFORMATION

encode input. ENC

can be taken above V

(up to 3.6V)

so 1.8V to 3.3V CMOS logic levels can be used. The ENC

threshold is 0.9V. For good jitter performance ENC

should

have fast rise and fall times. If the encode signal is turned

off or drops below approximately 500kHz, the A/D enters

nap mode.

Figure 12. Sinusoidal Encode Drive

ENC

–

PECL OR

LVDS

CLOCK

0.1µF

2271 F13

LTC2271

Figure 13. PECL or LVDS Encode Drive

50Ω

100Ω

0.1µF

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

50Ω

LTC2271

2271 F12

ENC

–

ENC

0.1µF

LTC2271

2271 F10

ENC

–

ENC

15k

DIFFERENTIAL

COMPARATOR

30k

Figure 10. Equivalent Encode Input Circuit

for Differential Encode Mode

30k

ENC

–

2271 F11

1.8V TO 3.3V

LTC2271

CMOS LOGIC

BUFFER

Figure 11. Equivalent Encode Input Circuit

for Single-Ended Encode Mode

Clock PLL and Duty Cycle Stabilizer

The encode clock is multiplied by an internal phase-locked

loop (PLL) to generate the serial digital output data. If the

encode signal changes frequency or is turned off, the PLL

requires 25µs to lock onto the input clock.

A clock duty cycle stabilizer circuit allows the duty cycle

of the applied encode signal to vary from 30% to 70%.

In the serial programming mode it is possible to disable

the duty cycle stabilizer, but this is not recommended. In

the parallel programming mode the duty cycle stabilizer

is always enabled.

2271f

LTC2271

APPLICATIONS INFORMATION

DIGITAL OUTPUTS

The digital outputs of the LTC2271 are serialized LVDS

signals. Each channel outputs one bit at a time (1-lane

mode), two bits at a time (2-lane mode) or four bits at a

time (4-lane mode). Please refer to the Timing Diagrams

for details. In 4-lane mode the clock duty cycle stabilizer

must be enabled.

The output data should be latched on the rising and falling

edges of the data clock out (DCO). A data frame output

(FR) can be used to determine when the data from a new

conversion result begins.

The minimum sample rate for all serialization modes is

5Msps.

By default the outputs are standard LVDS levels: 3.5mA

output current and a 1.25V output common mode volt-

age. An external 100 differential termination resistor

is required for each LVDS output pair. The termination

resistors should be located as close as possible to the

LVDS receiver.

The outputs are powered by OV

which is isolated from

the A/D core power.

Table 1. Maximum Sampling Frequency for All Serialization

Modes

SERIALIZATION

MODE

MAXIMUM

SAMPLING

FREQUENCY,

(MHz)

DCO

FREQUENCY

SERIAL

DATA RATE

4-Lane 20 2 • f

4 • f

2-Lane 20 4 • f

8 • f

1-Lane 20 8 • f

16 • f

Programmable LVDS Output Current

In LVDS mode, the default output driver current is 3.5mA.

This current can be adjusted by control register A2 in the

serial programming mode. Available current levels are

1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.

In the parallel programming mode the SDO pin can select

either 3.5mA or 1.75mA.

Optional LVDS Driver Internal Termination

In most cases using just an external 100 termination

resistor will give excellent LVDS signal integrity. In addi-

tion, an optional internal 100 termination resistor can

be enabled by serially programming mode control register

A2. The internal termination helps absorb any reﬂ ections

caused by imperfect termination at the receiver. When

the internal termination is enabled, the output driver

current is doubled to maintain the same output voltage

swing. Internal termination can only be selected in serial

programming mode.

DATA FORMAT

Table 2 shows the relationship between the analog input

voltage and the digital data output bits. By default the

output data format is offset binary. The 2’s complement

format can be selected by serially programming mode

control register A1.

Table 2. Output Codes vs Input Voltage

-A

–

(2V RANGE)

D15-D0

(OFFSET BINARY)

D15-D0

(2’ s COMPLEMENT)

>1.000000V

+0.999970V

+0.999939V

1111 1111 1111 1111

1111 1111 1111 1110

0111 1111 1111 1111

0111 1111 1111 1110

+0.000030V

+0.000000V

–0.000030V

–0.000061V

1000 0000 0000 0001

1000 0000 0000 0000

0111 1111 1111 1111

0111 1111 1111 1110

0000 0000 0000 0001

0000 0000 0000 0000

1111 1111 1111 1111

1111 1111 1111 1110

–0.999939V

–1.000000V

<–1.000000V

0000 0000 0000 0001

0000 0000 0000 0000

1000 0000 0000 0001

1000 0000 0000 0000

Digital Output Randomizer

Interference from the A/D digital outputs is sometimes

unavoidable. Digital interference may be from capacitive or

inductive coupling or coupling through the ground plane.

Even a tiny coupling factor can cause unwanted tones

in the ADC output spectrum. By randomizing the digital

output before it is transmitted off-chip, these unwanted

tones can be randomized which reduces the unwanted

tone amplitude.

LTC2271

2271f

The digital output is randomized by applying an exclusive

OR logic operation between the LSB and all other data

output bits. To decode, the reverse operation is applied—an

exclusive OR operation is applied between the LSB and all

other bits. The FR and DCO outputs are not affected. The

output randomizer is enabled by serially programming

mode control register A1.

Digital Output Test Pattern

To allow in-circuit testing of the digital interface to the

A/D, there is a test mode that forces the A/D data outputs

(D15-D0) of both channels to known values. The digital

output test patterns are enabled by serially programming

mode control registers A2, A3 and A4. When enabled,

the test patterns override all other formatting modes: 2’s

complement and randomizer.

Output Disable

The digital outputs may be disabled by serially program-

ming mode control register A2. The current drive for all

digital outputs including DCO and FR are disabled to save

power or enable in-circuit testing. When disabled the com-

mon mode of each output pair becomes high impedance,

but the differential impedance may remain low.

Sleep and Nap Modes

The A/D may be placed in sleep or nap modes to conserve

power. In sleep mode the entire device is powered down,

resulting in 1mW power consumption. Sleep mode is

enabled by mode control register A1 (serial program-

ming mode), or by SDI (parallel programming mode).

The amount of time required to recover from sleep mode

depends on the size of the bypass capacitors on V

REF

REFH and REFL. For the suggested values in Figure 8, the

A/D will stabilize after 2ms.

In nap mode any combination of A/D channels can be

powered down while the internal reference circuits and the

PLL stay active, allowing faster wake up than from sleep

mode. Recovering from nap mode requires at least 100

clock cycles. If the application demands very accurate DC

settling then an additional 50µs should be allowed so the

on-chip references can settle from the slight temperature

shift caused by the change in supply current as the A/D

leaves nap mode. Nap mode is enabled by mode control

DEVICE PROGRAMMING MODES

The operating modes of the LTC2271 can be programmed

by either a parallel interface or a simple serial interface.

The serial interface has more ﬂ exibility and can program

all available modes. The parallel interface is more limited

and can only program some of the more commonly used

modes.

Parallel Programming Mode

To use the parallel programming mode, PAR/SER should

be tied to V

. The CS, SCK, SDI and SDO pins are binary

logic inputs that set certain operating modes. These pins

can be tied to V

or ground, or driven by 1.8V, 2.5V or

3.3V CMOS logic. When used as an input, SDO should

be driven through a 1k series resistor. Table 3 shows the

modes set by CS, SCK, SDI and SDO.

Table 3. Parallel Programming Mode Control Bits (PAR/SER = V

)

PIN DESCRIPTION

CS/SCK 2-Lane/4-Lane/1-Lane Selection Bits

00 = 2-Lane Output Mode

01 = 4-Lane Output Mode

10 = 1-Lane Output Mode

11 = Not Used

SDI Power Down Control Bit

0 = Normal Operation

1 = Sleep Mode

SDO LVDS Current Selection Bit

0 = 3.5mA LVDS Current Mode

1 = 1.75mA LVDS Current Mode

Serial Programming Mode

To use the serial programming mode, PAR/SER should be

tied to ground. The CS, SCK, SDI and SDO pins become

a serial interface that program the A/D mode control

registers. Data is written to a register with a 16-bit serial

word. Data can also be read back from a register to verify

its contents.

Serial data transfer starts when CS is taken low. The data

on the SDI pin is latched at the ﬁ rst 16 rising edges of

SCK. Any SCK rising edges after the ﬁ rst 16 are ignored.

The data transfer ends when CS is taken high again.

APPLICATIONS INFORMATION

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

LTC2271CUKG#PBF

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Analog to Digital Converters - ADC 16-bit, 20Msps, 1.8V Low Noise Dual ADC, Serial LVDS Outputs

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LTC2271CUKG#PBF

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