1. General description
The 74AHC594; 74AHCT594 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC594; 74AHCT594 is an 8-bit, non-inverting, serial-in, parallel-out shift register
that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct
overriding clears (SHR and STR) are provided on both the shift and storage registers.
A serial output (Q7S) is provided for cascading purposes.
Both the shift and storage register clocks are positive-edge triggered. If the user wishes to
connect both clocks together, the shift register will always be one count pulse ahead of the
storage register.
2. Features
n Balanced propagation delays
n All inputs have Schmitt-trigger actions
n Inputs accept voltages higher than V
CC
n Wide supply voltage range from 2.0 V to 5.5 V
n 8-bit serial-in, parallel-out shift register with storage
n Independent direct overriding clears on shift and storage registers
n Independent clocks for shift and storage registers
n Latch-up performance exceeds 100 mA per JESD78 Class II
n Input levels:
u For 74AHC594: CMOS level
u For 74AHCT594: TTL level
n ESD protection:
u HBM EIA/JESD22-A114E exceeds 2000 V
u MM EIA/JESD22-A115-A exceeds 200 V
u CDM EIA/JESD22-C101C exceeds 1000 V
n Multiple package options
n Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Applications
n Serial-to parallel data conversion
n Remote control holding register
74AHC594; 74AHCT594
8-bit shift register with output register
Rev. 02 — 9 June 2008 Product data sheet
