74AHC_AHCT594_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 9 June 2008 5 of 22
NXP Semiconductors
74AHC594; 74AHCT594
8-bit shift register with output register
6.2 Pin description
7. Functional description
[1] H = HIGH voltage state;
L = LOW voltage state;
↑ = LOW to HIGH transition;
X = don’t care;
NC = no change;
Table 2. Pin description
Symbol Pin Description
Q1 1 parallel data output
Q2 2 parallel data output
Q3 3 parallel data output
Q4 4 parallel data output
Q5 5 parallel data output
Q6 6 parallel data output
Q7 7 parallel data output
GND 8 ground (0 V)
Q7S 9 serial data output
SHR 10 shift register reset input (active LOW)
SHCP 11 shift register clock input
STCP 12 storage register clock input
STR 13 storage register reset input (active LOW)
DS 14 serial data input
Q0 15 parallel data output
V
CC
16 supply voltage
Table 3. Function table
[1]
Input Output Function
SHCP STCP SHR STR DS Q7S Qn
X X L X X L NC a LOW-state on
SHR only affects the shift register
X X X L X NC L a LOW-state on
STR only affects the storage register
X ↑ L H X L L empty shift register loaded into storage register
↑ X H X H Q6S NC logic HIGH level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
X ↑ H H X NC QnS contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
↑↑H H X Q6S QnS contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
