Data Sheet AD7400
Rev. G | Page 3 of 20
SPECIFICATIONS
V
DD1
= 4.5 V to 5.25 V, V
DD2
= 3 V to 5.5 V, V
IN
+ = −200 mV to +200 mV, and V
IN
− = 0 V (single-ended); T
A
= T
MIN
to T
MAX
,
f
MCLK
= 10 MHz, tested with Sinc
3
filter, 256 decimation rate, as defined by Verilog code, unless otherwise noted.
1
Table 1.
Parameter Y Version
1, 2
Unit Test Conditions/Comments
Resolution
16 Bits min Filter output truncated to 16 bits
Integral Nonlinearity
3
±15 LSB max −40°C to +85°C; ±2 LSB typical
±25 LSB max >85°C to 105°C
Differential Nonlinearity
3
±0.9 LSB max Guaranteed no missing codes to 16 bits
3
±50 µV typ T
A
= 25°C
Offset Drift vs. Temperature
3.5 µV/°C max −40°C to +105°C
1 µV/°C typ
Offset Drift vs. V
DD1
120 µV/V typ
Gain Error
3
±1 mV max
Gain Error Drift vs. Temperature 23 µV/°C typ −40°C to +105°C
Gain Error Drift vs. V
DD1
110 µV/V typ
ANALOG INPUT
For specified performance; full range ±320 mV
Dynamic Input Current ±8 µA max V
IN
+ = 400 mV, V
IN
− = 0 V
±0.5 µA typ V
IN
+ = V
IN
− = 0 V
Input Capacitance 10 pF typ
DYNAMIC SPECIFICATIONS V
IN
+ = 35 Hz, 400 mV p-p sine
Signal-to-(Noise + Distortion) Ratio (SINAD)
3
70 dB min −40°C to +85°C
65 dB min >85°C to 105°C
79 dB typ
Signal-to-Noise Ratio (SNR) 71 dB min −40°C to +105°C
Total Harmonic Distortion (THD)
3
−88 dB typ
Peak Harmonic or Spurious Noise (SFDR)
3
−88 dB typ
Effective Number of Bits (ENOB)
3
11.5 Bits
Isolation Transient Immunity
3
25 kV/µs min
30 kV/µs typ
LOGIC OUTPUTS
Output High Voltage, V
OH
V
DD2
− 0.1 V min I
O
= −200 µA
Output Low Voltage, V
OL
0.4 V max I
O
= +200 µA
POWER REQUIREMENTS
V
DD1
4.5/5.25 V min/V max
V
DD2
3/5.5 V min/V max
I
DD1
4
13 mA max V
DD1
= 5.25 V
I
DD2
5
6 mA max V
DD2
= 5.5 V
4 mA max V
DD2
= 3.3 V
1
Temperature range is −40°C to +85°C.
2
All voltages are relative to their respective ground.
3
See the Terminology section.
4
See Figure 14.
5
See Figure 15.
