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CY7C024E-15AXC

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
CY7C024E
CY7C025E
CY7C0251E
Document Number: 001-62932 Rev. *G Page 10 of 24
Data Retention Mode
The CY7C024E is designed with battery backup in mind. Data
retention voltage and supply current are guaranteed over
temperature. The following rules insure data retention:
1. Chip enable (CE
) must be held HIGH during data retention,
within V
CC
to V
CC
– 0.2 V.
2. CE
must be kept between V
CC
– 0.2 V and 70% of V
CC
during
the power up and power down transitions.
3. The RAM can begin operation >t
RC
after V
CC
reaches the
minimum operating voltage (4.5 V).
Capacitance
Parameter
[17]
Description Test Conditions Max Unit
C
IN
Input capacitance T
A
= 25 °C , f = 1 MHz,
V
CC
= 5.0 V
10 pF
C
OUT
Output capacitance 10 pF
Figure 3. AC Test Loads and Waveforms
3.0 V
GND
90%
90%
10%
3ns
3
ns
10%
ALL INPUTPULSES
(a) Normal Load (Load 1)
R1 = 893
5 V
OUTPUT
R2 = 347
C= 30
pF
V
TH
= 1.4 V
OUTPUT
C=
30 pF
(b) Thévenin Equivalent (Load 1)
(c) Three-State Delay(Load
3)
C= 30pF
OUTPUT
Load (Load 2)
R1 = 893
R2 = 347
5 V
OUTPUT
C= 5pF
R
TH
=250
Data Retention Timing
Parameter Test Conditions
[18]
Max Unit
ICC
DR1
At VCC
DR
= 2 V 1.5 mA
Data Retention Mode
4.5 V
4.5 V
V
CC
2.0 V
V
CC
to V
CC
– 0.2 V
V
CC
CE
t
RC
V
IH
Note
17. Tested initially and after any design or process changes that may affect these parameters.
18. CE
= V
CC
, V
in
= GND to V
CC
, T
A
= 25C. This parameter is guaranteed but not tested.
CY7C024E
CY7C025E
CY7C0251E
Document Number: 001-62932 Rev. *G Page 11 of 24
Switching Characteristics
Over the Operating Range
Parameter
[19]
Description
-15 -25 -55
Unit
Min Max Min Max Min Max
Read Cycle
t
RC
Read cycle time 15 – 25 – 55 – ns
t
AA
Address to data valid – 15 – 25 – 55 ns
t
OHA
Output hold from address change 3 – 3 – 3 – ns
t
ACE
[20]
CE LOW to data valid – 15 – 25 – 55 ns
t
DOE
OE LOW to data valid – 10 – 13 – 25 ns
t
LZOE
[21, 22, 23]
OE low to low Z 3 – 3 – 3 – ns
t
HZOE
[21, 22, 23]
OE HIGH to high Z – 10 – 15 – 25 ns
t
LZCE
[21, 22, 23]
CE LOW to low Z 3 – 3 – 3 – ns
t
HZCE
[21, 22, 23]
CE HIGH to High Z – 10 – 15 – 25 ns
t
PU
[23]
CE LOW to power-up 0 – 0 – 0 – ns
t
PD
[23]
CE HIGH to power-down – 15 – 25 – 55 ns
t
ABE
[20]
Byte enable access time – 15 – 25 – 55 ns
Write Cycle
t
WC
Write cycle time 15 – 25 – 55 – ns
t
SCE
[20]
CE LOW to write end 12 – 20 – 35 – ns
t
AW
Address setup to write end 12 – 20 – 35 – ns
t
HA
Address hold from write end 0 – 0 – 0 – ns
t
SA
[24]
Address setup to write start 0 – 0 – 0 – ns
t
PWE
Write pulse width 12 – 20 – 35 – ns
t
SD
Data setup to write end 10 – 15 – 20 – ns
t
HD
Data hold from write end 0 – 0 – 0 – ns
t
HZWE
[25, 26]
R/W LOW to high Z – 10 – 15 – 25 ns
t
LZWE
[25, 26]
R/W HIGH to low Z 3 – 3 – 3 – ns
t
WDD
[27]
Write pulse to data delay – 30 – 50 – 70 ns
t
DDD
[27]
Write data valid to read
data valid
–25–35 –45ns
Notes
19. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified I
OI
/I
OH
and 30 pF load capacitance.
20. To access RAM, CE
=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
SCE
time.
21. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
22. Test conditions used are Load 3.
23. This parameter is guaranteed but not tested.
24. To access RAM, CE
=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire t
SCE
time.
25. Test conditions used are Load 3.
26. This parameter is guaranteed but not tested.
27. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11 on page 16.
CY7C024E
CY7C025E
CY7C0251E
Document Number: 001-62932 Rev. *G Page 12 of 24
Busy Timing
[28]
t
BLA
BUSY LOW from Address Match – 15 – 20 – 45 ns
t
BHA
BUSY HIGH from Address
Mismatch
–15–20 –40ns
t
BLC
BUSY LOW from CE LOW – 15 – 20 – 40 ns
t
BHC
BUSY HIGH from CE HIGH –15–20 –35ns
t
PS
Port Setup for Priority 5 – 5 – 5 – ns
t
WB
R/W HIGH after BUSY (Slave) 0 – 0 – 0 – ns
t
WH
R/W HIGH after BUSY HIGH (Slave) 13 – 20 – 40 – ns
t
BDD
[29]
BUSY HIGH to Data Valid – Note 29 Note 29 Note 29 ns
Interrupt Timing
[28]
t
INS
INT Set Time –15–20 –30ns
t
INR
INT Reset Time –15–20 –30ns
Semaphore Timing
t
SOP
SEM Flag Update Pulse (OE or SEM)10 – 12 – 20 – ns
t
SWRD
SEM Flag Write to Read Time 5 – 10 – 15 – ns
t
SPS
SEM Flag Contention Window 5 – 10 – 15 – ns
t
SAA
SEM Address Access Time – 15 25 – 55 ns
Switching Characteristics (continued)
Over the Operating Range
Parameter
[19]
Description
-15 -25 -55
Unit
Min Max Min Max Min Max
Notes
28. Test conditions used are Load 2.
29. t
BDD
is a calculated parameter and is the greater of t
WDD
– t
PWE
(actual) or t
DDD
– t
SD
(actual).
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CY7C024E-15AXC

Mfr. #:
Buy CY7C024E-15AXC
Manufacturer:
Cypress Semiconductor
Description:
SRAM 64Kb 15ns 4K x 16 Dual Port SRAM
Lifecycle:
New from this manufacturer.
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