PC Board Layout Guidelines
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The
switching power stage requires particular attention. If
possible, mount all the power components on the top
side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
1) Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
2) Connect the power and analog grounds close to
the IC.
3) The IC needs two bypassing ceramic capacitors for
input and supply. C1 isolates the IC from current
pulses at N1, and should be placed such that the
path between C1 and N1 is not shared with the IC.
C7 bypasses the IC and should be placed adjacent
to the IC.
4) Keep the power traces and load connections short.
This practice is essential for high efficiency. Using
thick copper PC boards (2oz vs. 1oz) can enhance
full-load efficiency by 1% or more. Correctly routing
PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a few milliwatts of excess trace resistance
cause a measurable efficiency penalty.
5) LX and GND connections to N2 for current sensing
must be made using Kelvin sense connections to
guarantee the current-limit accuracy. With 8-pin SO
MOSFETs, this is best done by routing power to the
MOSFETs from the outside using the top copper
layer, while connecting LX and GND inside (under-
neath) the 8-pin SO package.
6) When tradeoffs in trace lengths must be made, it is
preferable to allow the inductor charging current
path to be longer than the discharge path. For
example, it is better to allow some extra distance
between the inductor and the low-side MOSFET or
between the inductor and the output filter capacitor.
7) Ensure that the connection between the inductor
and C3 is short and direct.
8) Route switching nodes (BST, LX, DH, and DL) away
from sensitive analog areas (COMP, FB).
9) Ensure that the C1 ceramic bypass capacitor is
immediately adjacent to the pins and as close to
the device as possible. Furthermore, the V
IN
and
GND pins of MAX1966/MAX1967 must terminate at
the two ends of C1 before connecting to the power
switches and C2.
Layout Procedure
1) Place the power components first, with ground ter-
minals adjacent (N2 source, C2, C3). If possible,
make all these connections on the top layer with
wide, copper-filled areas.
2) Mount the MAX1966/MAX1967 adjacent to MOSFET
N2, preferably on the backside opposite N2 in
order to keep LX, GND, and the DL gate-drive lines
short and wide. The DL gate trace must be short
and wide measuring 50mils to 100mils wide if the
MOSFET is 1in from the MAX1966/MAX1967.
3) The V
IN
and GND pins of MAX1966/MAX1967 must
terminate at the two ends of C1 before connecting
to the power switches and C2. C1’s ground con-
nection must be as close to the IC’s GND pin as
possible.
4) On MAX1966, C7 must be connected to the VIN
and GND pins with mimimum distance. On the
MAX1967, C7 must be connected to VL and GND
pins with minimum distance.
5) Group the gate-drive components (BST diode and
C5) together near the controller IC.
6) Make the MAX1966/MAX1967 ground connections
to three separate ground planes: the output ground
plane, where all the high-power components con-
nect; the power ground plane, where the output
bypass capacitor C3 connects; and the analog
ground plane, where sensitive analog components
connect. The analog ground plane and power
ground plane must meet only at a single point
directly beneath the IC. These two planes are then
connected to the high-power output ground with a
short connection for the C3 capacitor to the source
of the low-side MOSFET, N2 (the middle of the star
ground). This point must also be very close to the
output capacitor ground terminal.
Refer to the MAX1966/MAX1967 EV kit manual for a PC
board layout example.
MAX1966/MAX1967
Low-Cost Voltage Mode PWM
Step-Down Controller
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