PIC16 with SSP Module and
PIC17 Interface
The MAX1062 is compatible with a PIC16/PIC17 micro-
controller (µC) using the synchronous serial-port (SSP)
module.
To establish SPI communication, connect the controller
as shown in Figure 12a. Configure the PIC16/PIC17 as
system master, by initializing its synchronous serial-port
control register (SSPCON) and synchronous serial-port
status register (SSPSTAT) to the bit patterns shown in
Tables 1 and 2.
In SPI mode, the PIC16/PIC17 µC allows 8 bits of data
to be synchronously transmitted and received simulta-
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
______________________________________________________________________________________ 13
CS
QSPI
SCLK
DOUT
CS
SCK
MISO
V
DD
SS
MAX1062
SCK
SDI
GND
PIC16/17
I/O
SCLK
DOUT
CS
V
DD
V
DD
MAX1062
Figure 11a. QSPI Connections
Figure 12a. SPI Interface Connection for a PIC16/PIC17
DOUT*
CS
SCLK
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
2016
D13 D12 D11
D10 D9 D8 D7
HIGH-Z
S1 S0
24
1214 86
D6 D3 D2 D1
LSB
D5 D4
END OF
ACQUISITION
D0
Figure 11b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
CONTROL BIT
MAX1062
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPCON)
WCOL BIT7 X Write Collision Detection Bit
SSPOV BIT6 X Receive Overflow Detect Bit
SSPEN BIT5 1
Synchronous Serial-Port Enable Bit:
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
CKP BIT4 0 Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3 BIT3 0
SSPM2 BIT2 0
SSPM1 BIT1 0
SSPM0 BIT0 1
Synchronous Serial-Port Mode Select Bit. Sets SPI master mode and selects
f
CLK
= f
OSC
/ 16.
Table 1. Detailed SSPCON Register Contents
X = Don’t care
MAX1062
neously. Three consecutive 8-bit readings (Figure 12b)
are necessary to obtain the entire 14-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the µC on SCLK’s rising edge.
The first 8-bit data stream contains all zeros. The sec-
ond 8-bit data stream contains the MSB through D6.
The third 8-bit data stream contains bits D5 through D0
followed by S1 and S0.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-fit straight line fit or a
line drawn between the end points of the transfer func-
tion, once offset and gain errors have been nullified.
The static linearity parameters for the MAX1062 are
measured using the endpoint method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of 1LSB guarantees no missing
codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (t
AJ
) is the sample-to-sample variation in
the time between samples. Aperture delay (t
AD
) is the
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
14 ______________________________________________________________________________________
CONTROL BIT
MAX1062
SETTINGS
SYNCHRONOUS SERIAL-PORT CONTROL REGISTER (SSPSTAT)
SMP BIT7 0 SPI Data Input Sample Phase. Input data is sampled at the middle of the data output time.
CKE BIT6 1
SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the
serial clock.
D/A BIT5 X Data Address Bit
P BIT4 X Stop Bit
S BIT3 X Start Bit
R/W BIT2 X Read/Write Bit Information
UA BIT1 X Update Address
BF BIT0 X Buffer Full Status Bit
Table 2. Detailed SSPSTAT Register Contents
DOUT*
CS
SCLK
1ST BYTE READ
2ND BYTE READ
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
HIGH-Z
3RD BYTE READ
LSB
S1 S0D5 D4 D3 D2 D1 D0
2420
1612
D13 D12 D11 D10 D9 D8 D7 D6
00 0 000 00
D5
Figure 12b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 =0001)
X = Don’t care
time between the falling edge of the sampling clock
and the instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADCs res-
olution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals.
Effective Number of Bits
Effective number of bits (ENOB) indicate the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC error consists of quantiza-
tion noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
ENOB = (SINAD – 1.76) / 6.02
Figure 13 shows the effective number of bits as a func-
tion of the MAX1062’s input frequency.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V
1
is the fundamental amplitude and V
2
through
V
5
are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest fre-
quency component.
Supplies, Layout, Grounding
and Bypassing
Use PC boards with separate analog and digital
ground planes. Do not use wire-wrap boards. Connect
the two ground planes together at the MAX1062 (pin 3).
Isolate the digital supply from the analog with a low-
value resistor (10) or ferrite bead when the analog
and digital supplies come from the same source
(Figure 14).
THD
VVVV
V
+++
20
1
2
2
3
2
4
2
5
2
log
SINAD dB
Signal
Noise Distortion
RMS
RMS
( ) log
+
()
20
MAX1062
14-Bit, +5V, 200ksps ADC with 10µA Shutdown
______________________________________________________________________________________ 15
0.1 10 100
MAX1062 Fig13
INPUT FREQUENCY (kHz)
EFFECTIVE BITS
1
14
0
2
4
6
8
12
10
f
SAMPLE
= 200kHz
Figure 13. Effective Bits vs. Input Frequency
SCLK
DOUT
AGND
DGND
AIN
10
REF
AV
DD
DV
DD
DOUT
SCLK
CS
AIN
V
REF
+5V
4.7µF
0.1µF
0.1µF
GND
MAX1062
CS
Figure 14. Powering AV
DD
and DV
DD
from a Single Supply

MAX1062BEUB+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 5V 14-Bit 200ksp w/10uA Shutdown
Lifecycle:
New from this manufacturer.
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