MAX1062BEUB+T Datasheet MAX1062CCUB+, MAX1062BEUB+, MAX1062ACUB+ | P10-P12

MAX1062

Output Coding and

Transfer Function

The data output from the MAX1062 is binary and Figure

8 depicts the nominal transfer function. Code transitions

occur halfway between successive-integer LSB values

REF

= 4.096V and 1LSB = 250µV or 4.096V/16384).

Applications Information

External Reference

The MAX1062 requires an external reference with a

voltage range between 3.8V and AV

. Connect the

external reference directly to REF. Bypass REF to

AGND (pin 3) with a 4.7µF capacitor. When not using a

low ESR bypass capacitor, use a 0.1µF ceramic capac-

itor in parallel with the 4.7µF capacitor. Noise on the

reference degrades conversion accuracy.

The input impedance at REF is 40kΩ for DC currents.

During a conversion the external reference at REF must

deliver 100µA of DC load current and have an output

impedance of 10Ω or less.

For optimal performance, buffer the reference through

an op amp and bypass the REF input. Consider the

MAX1062’s equivalent input noise (80µV

RMS

) when

choosing a reference.

Input Buffer

Most applications require an input buffer amplifier to

achieve 14-bit accuracy. If the input signal is multi-

plexed, switch the input channel immediately after acqui-

sition, rather than near the end of or after a conversion

(Figure 9). This allows the maximum time for the input

buffer amplifier to respond to a large step change in the

input signal. The input amplifier must have a slew rate of

at least 2V/µs to complete the required output voltage

change before the beginning of the acquisition time.

At the beginning of the acquisition, the internal sampling

capacitor array connects to AIN (the amplifier output),

causing some output disturbance. Ensure that the sam-

pled voltage has settled before the end of the acquisition

time.

Digital Noise

Digital noise can couple to AIN and REF. The conver-

sion clock (SCLK) and other digital signals active dur-

ing input acquisition contribute noise to the conversion

result. Noise signals synchronous with the sampling

interval result in an effective input offset. Asynchronous

signals produce random noise on the input, whose

14-Bit, +5V, 200ksps ADC with 10µA Shutdown

10 ______________________________________________________________________________________

COMPLETE CONVERSION SEQUENCE

CONVERSION 0

CONVERSION 1

POWERED UPPOWERED UP POWERED DOWN

DOUT

Figure 7. Shutdown Sequence

OUTPUT CODE

FULL-SCALE

TRANSITION

11 . . . 111

11 . . . 110

11 . . . 101

00 . . . 011

00 . . . 010

00 . . . 001

00 . . . 000

123

FS - 3/2LSB

FS = V

REF

INPUT VOLTAGE (LSB)

1LSB =

REF

16384

Figure 8. Unipolar Transfer Function, Full Scale (FS) = V

REF

Zero Scale (ZS) = GND

high-frequency components may be aliased into the

frequency band of interest. Minimize noise by present-

ing a low impedance (at the frequencies contained in

the noise signal) at the inputs. This requires bypassing

AIN to AGND, or buffering the input with an amplifier

that has a small-signal bandwidth of several MHz, or

preferably both. AIN has about 4MHz of bandwidth.

Distortion

Avoid degrading dynamic performance by choosing an

amplifier with distortion much less than the MAX1062’s

total harmonic distortion (THD = -99dB at 1kHz) at fre-

quencies of interest. If the chosen amplifier has insuffi-

cient common-mode rejection, which results in

degraded THD performance, use the inverting configu-

ration (positive input grounded) to eliminate errors from

this source. Low temperature-coefficient, gain-setting

resistors reduce linearity errors caused by resistance

changes due to self-heating. To reduce linearity errors

due to finite amplifier gain, use amplifier circuits with

sufficient loop gain at the frequencies of interest.

DC Accuracy

To improve DC accuracy, choose a buffer with an offset

much less than the MAX1062’s offset (1mV (max) for +5V

supply), or whose offset can be trimmed while maintain-

ing stability over the required temperature range.

Serial Interfaces

The MAX1062’s interface is fully compatible with SPI,

QSPI, and MICROWIRE standard serial interfaces.

If a serial interface is available, establish the CPU’s ser-

ial interface as master, so that the CPU generates the

serial clock for the MAX1062. Select a clock frequency

between 100kHz and 4.8MHz:

1) Use a general-purpose I/O line on the CPU to pull

CS low.

2) Activate SCLK for a minimum of 24 clock cycles.

The serial data stream of eight leading zeros fol-

lowed by the MSB of the conversion result begins at

the falling edge of CS. DOUT transitions on SCLK’s

falling edge and the output is available in MSB-first

MAX1062

14-Bit, +5V, 200ksps ADC with 10µA Shutdown

______________________________________________________________________________________ 11

CLK

CHANGE MUX INPUT HERE

CONVERSION

IN1

A0 A1

IN2

IN3

IN4

OUT

ACQUISITION

4-TO-1

MUX

AIN

MAX1062

Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling

MAX1062

format. Observe the SCLK to DOUT valid timing

characteristic. Clock data into the µP on SCLK’s ris-

ing edge.

3) Pull CS high at or after the 24th falling clock edge. If

CS remains low, trailing zeros are clocked out after

the 2 sub-bits, S1 and S0.

4) With CS high, wait at least 50ns (t

CSW

) before start-

ing a new conversion by pulling CS low. A conver-

sion can be aborted by pulling CS high before the

conversion ends. Wait at least 50ns before starting a

new conversion.

Data can be output in three 8-bit sequences or continu-

ously. The bytes contain the results of the conversion

padded with eight leading zeros before the MSB. If the

serial clock has not been idled after the sub-bits (S1

and S0) and CS has been kept low, DOUT sends trail-

ing zeros.

SPI and MICROWIRE Interfaces

When using the SPI (Figure 10a) or MICROWIRE

(Figure 10b) interfaces, set CPOL = 0 and CPHA = 0.

Conversion begins with a falling edge on CS (Figure

10c). Three consecutive 8-bit readings are necessary

to obtain the entire 14-bit result from the ADC. DOUT

data transitions on the serial clock’s falling edge. The

first 8-bit data stream contains all leading zeros. The

second 8-bit data stream contains the MSB through D6.

The third 8-bit data stream contains D5 through D0 fol-

lowed by S1 and S0.

QSPI Interface

Using the high-speed QSPI interface with CPOL = 0

and CPHA = 0, the MAX1062 supports a maximum

SCLK

of 4.8MHz. Figure 11a shows the MAX1062 con-

nected to a QSPI master and Figure 11b shows the

associated interface timing.

14-Bit, +5V, 200ksps ADC with 10µA Shutdown

12 ______________________________________________________________________________________

SCLK

DOUT

I/O

SCK

MISO

SPI

MAX1062

Figure 10a. SPI Connections

MAX1067

MAX1068

MICROWIRE

SCLK

DOUT

I/O

Figure 10b. MICROWIRE Connections

DOUT*

SCLK

1ST BYTE READ

2ND BYTE READ

*WHEN CS IS HIGH, DOUT = HIGH-Z

MSB

HIGH-Z

3RD BYTE READ

LSB

S1 S0D5 D4 D3 D2 D1 D0

2420

1612

641

D13 D12 D11 D10 D9 D8 D7 D6 D5

00 0 000 00

Figure 10c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA =0)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MAX1062BEUB+T

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Analog to Digital Converters - ADC 5V 14-Bit 200ksp w/10uA Shutdown

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MAX1062BEUB+T

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