MC14106BDG

© Semiconductor Components Industries, LLC, 2014
August, 2014 − Rev. 10
1 Publication Order Number:
MC14106B/D
MC14106B
Hex Schmitt Trigger
The MC14106B hex Schmitt Trigger is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14106B
may be used in place of the MC14069UB hex inverter for enhanced
noise immunity or to “square up” slowly changing waveforms.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However, precautions
must be taken to avoid applications of any voltage higher than
maximum rated voltages to this high−impedance circuit. For proper
operation, V
in
and V
out
should be constrained to the range V
SS
(V
in
or V
out
) V
DD
.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either V
SS
or V
DD
). Unused outputs must be left open.
Features
Increased Hysteresis Voltage Over the MC14584B
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−power TTL Loads or One
Low−power Schottky TTL Load Over the Rated Temperature
Range
Pin−for−Pin Replacement for CD40106B and MM74C14
Can Be Used to Replace the MC14584B or MC14069UB
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to V
SS
)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage Range 0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
0.5 to V
DD
+ 0.5 V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
± 10 mA
P
D
Power Dissipation, per Package
(Note 1)
500 mW
T
A
Ambient Temperature Range 55 to +125 °C
T
stg
Storage Temperature Range 65 to +150 °C
T
L
Lead Temperature
(8−Second Soldering)
260 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/°C From 65°C To 125°C
http://onsemi.com
MARKING DIAGRAMS
SOIC−14 NB
TSSOP−14
1
14
14106BG
AWLYWW
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
14
106B
ALYWG
G
1
14
(Note: Microdot may be in either location)
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
MC14106B
http://onsemi.com
2
Figure 1. Logic Diagram
13 12
10
8
6
4
2
11
9
5
3
1
V
DD
= PIN 14
V
SS
= PIN 7
Figure 2. Equivalent Circuit Schematic
(1/6 of Circuit Shown)
ORDERING INFORMATION
Device Package Shipping
MC14106BDG SOIC−14 NB
(Pb−Free)
55 Units / Rail
NLV14106BDG* SOIC−14 NB
(Pb−Free)
55 Units / Rail
MC14106BDR2G SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
NLV14106BDR2G* SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
MC14106BDTR2G TSSOP−14
(Pb−Free)
2500 / Tape & Reel
NLV14106BDTR2G* TSSOP−14
(Pb−Free)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
MC14106B
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (Voltages Referenced to V
SS
)
Characteristic
Symbo
l
V
DD
Vdc
−55°C 25°C 125°C
Unit
Min Max Min
Typ
(Note 2)
Max Min Max
Output Voltage “0” Leve
l
V
in
= V
DD
“1” Leve
l
V
in
= 0
V
OL
5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
V
OH
5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Hysteresis Voltage V
H
(5)
5.0
10
15
0.3
1.2
1.6
2.0
3.4
5.0
0.3
1.2
1.6
1.1
1.7
2.1
2.0
3.4
5.0
0.3
1.2
1.6
2.0
3.4
5.0
Vdc
Threshold Voltage
Positive−Going
Negative−Going
V
T+
5.0
10
15
2.2
4.6
6.8
3.6
7.1
10.8
2.2
4.6
6.8
2.9
5.9
8.8
3.6
7.1
10.8
2.2
4.6
6.8
3.6
7.1
10.8
Vdc
V
T–
5.0
10
15
0.9
2.5
4.0
2.8
5.2
7.4
0.9
2.5
4.0
1.9
3.9
5.8
2.8
5.2
7.4
0.9
2.5
4.0
2.8
5.2
7.4
Vdc
Output Drive Current
(V
OH
= 2.5 Vdc) Source
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc) Sin
k
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
I
OH
5.0
5.0
10
15
–3.0
–0.64
–1.6
–4.2
–2.4
–0.51
–1.3
–3.4
–4.2
–0.88
–2.25
–8.8
–1.7
–0.36
–0.9
–2.4
mAdc
I
OL
5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current I
in
15 ±0.1 ± 0.00001 ±0.1 ±1.0
mAdc
Input Capacitance
(V
in
= 0)
C
in
5.0 7.5 pF
Quiescent Current
(Per Package)
I
DD
5.0
10
15
0.25
0.5
1.0
0.0005
0.0010
0.0015
0.25
0.5
1.0
7.5
15
30
mAdc
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
5.0
10
15
I
T
= (1.8 mA/kHz) f + I
DD
I
T
= (3.6 mA/kHz) f + I
DD
I
T
= (5.4 mA/kHz) f + I
DD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25°C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk where I
T
is in mA (per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and
k = 0.001.
5. V
H
=
V
T+
V
T–
(But maximum variation of V
H
is specified as less that V
T+
max
– V
T–
min
).

MC14106BDG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Inverters 3-18V CMOS Hex Schmitt Trigger
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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