74LVC1G86GW-Q100H

74LVC1G86-Q100
2-input EXCLUSIVE-OR gate
Rev. 3 — 7 March 2017 Product data sheet
1 General description
The 74LVC1G86-Q100 provides the 2-input EXCLUSIVE-OR function.
Inputs can be driven from either 3.3 V or 5 V devices. These features allow the use of
these devices in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial Power-down applications using I
OFF
. The I
OFF
circuitry disables the output, preventing the damaging backflow current through the
device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2 Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
±24 mA output drive (V
CC
= 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Nexperia
74LVC1G86-Q100
2-input EXCLUSIVE-OR gate
74LVC1G86_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 7 March 2017
2 / 13
3 Ordering information
Table 1. Ordering information
PackageType number
Temperature
range
Name Description Version
74LVC1G86GW-Q100 -40 °C to +125 °C TSSOP5 plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74LVC1G86GV-Q100 -40 °C to +125 °C SC-74A plastic surface-mounted package; 5 leads SOT753
4 Marking
Table 2. Marking codes
Type number Marking
[1]
74LVC1G86GW-Q100 VH
74LVC1G86GV-Q100 V86
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5 Functional diagram
mna038
B
A
Y
2
1
4
Figure 1. Logic symbol
1
2
= 1
4
mna039
Figure 2. IEC logic symbol
mna040
Y
B
A
Figure 3. Logic diagram
6 Pinning information
6.1 Pinning
74LVC1G86-Q100
B V
CC
A
GND Y
aaa-009532
1
2
3
5
4
Figure 4. Pin configuration SOT353-1 and SOT753
Nexperia
74LVC1G86-Q100
2-input EXCLUSIVE-OR gate
74LVC1G86_Q100 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 7 March 2017
3 / 13
6.2 Pin description
Table 3. Pin description
Symbol Pin Description
B 1 data input
A 2 data input
GND 3 ground (0 V)
Y 4 data output
V
CC
5 supply voltage
7 Functional description
Table 4. Function table
[1]
Input Output
A B Y
L L L
L H H
H L H
H H L
[1] H = HIGH voltage level;
L = LOW voltage level
8 Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage -0.5 +6.5 V
I
IK
input clamping current V
I
< 0 V -50 - mA
V
I
input voltage
[1]
-0.5 +6.5 V
I
OK
output clamping current V
O
> V
CC
or V
O
< 0 V - ±50 mA
Active mode
[1]
[2]
-0.5 V
CC
+ 0.5 VV
O
output voltage
Power-down mode
[1]
[2]
-0.5 +6.5 V
I
O
output current V
O
= 0 V to V
CC
- ±50 mA
I
CC
supply current - +100 mA
I
GND
ground current -100 - mA
P
tot
total power dissipation T
amb
= -40 °C to +125 °C
[3]
- 250 mW
T
stg
storage temperature -65 +150 °C
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When V
CC
= 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 °C the value of P
tot
derates linearly with 4.0 mW/K.

74LVC1G86GW-Q100H

Mfr. #:
Manufacturer:
Nexperia
Description:
Logic Gates 74LVC1G86GW-Q100/UMT5/REEL 7
Lifecycle:
New from this manufacturer.
Delivery:
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