MAX1165/MAX1166
Selecting Standby or Shutdown Mode
The MAX1165/MAX1166 have a selectable standby or
low-power shutdown mode. In standby mode, the
ADC’s internal reference and reference buffer do not
power down between conversions, eliminating the need
to wait for the reference to power up before performing
the next conversion. Shutdown mode powers down the
reference and reference buffer after completing a con-
version. The reference and reference buffer require a
minimum of 10ms (C
REFADJ
= 0.1µF, C
REF
= 4.7µF) to
power up and settle from shutdown.
The state of R/C at the second falling edge of CS
selects which power-down mode the MAX1165/
MAX1166 enter upon conversion completion. Holding
R/C low causes the MAX1165/MAX1166 to enter stand-
by mode. The reference and buffer are left on after the
conversion completes. R/C high causes the MAX1165/
MAX1166 to enter shutdown mode and shut down the
reference and buffer after conversion (Figures 5 and 6).
When using an external reference, set the REF power-
down bit high for lowest current operation.
Standby Mode
While in standby mode, the supply current is reduced
to less than 1mA (typ). The next falling edge of CS with
R/C low causes the MAX1165/MAX1166 to exit standby
mode and begin acquisition. The reference and refer-
ence buffer remain active to allow quick turn-on time.
Standby mode allows significant power savings while
running at the maximum sample rate.
Shutdown Mode
In shutdown mode, the reference and reference buffer
are shut down between conversions. Shutdown mode
reduces supply current to 0.5µA (typ) immediately after
the conversion. The falling edge of CS with R/C low
causes the reference and buffer to wake up and enter
acquisition mode. To achieve 16-bit accuracy, allow
10ms (C
REFADJ
= 0.1µF, C
REF
= 4.7µF) for the internal
reference to wake up.
Internal and External Reference
Internal Reference
The internal reference of the MAX1165/MAX1166 is
internally buffered to provide +4.096V output at REF.
Bypass REF to AGND and REFADJ to AGND with 4.7µF
and 0.1µF, respectively.
Fine adjustments can be made to the internal reference
voltage by sinking or sourcing current at REFADJ. The
input impedance of REFADJ is nominally 5k. The
internal reference voltage is adjustable to ±1.5% with
the circuit of Figure 7.
External Reference
An external reference can be placed at either the input
(REFADJ) or the output (REF) of the MAX1165/
MAX1166s’ internal buffer amplifier. When connecting an
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
10 ______________________________________________________________________________________
CS
REF
AND
BUFFER
REF POWER-
DOWN BIT
ACQUISITION
CONVERSION
DATA
OUT
R/C
EOC
Figure 5. Selecting Standby Mode
REF POWER-
DOWN BIT
ACQUISITION
CONVERSION
DATA
OUT
CS
REF
AND
BUFFER
R/C
EOC
Figure 6. Selecting Shutdown Mode
MAX1165
MAX1166
REFADJ
+5V
100k
150k
68k
0.1µF
Figure 7. MAX1165/MAX1166 Reference Adjust Circuit
external reference to REFADJ, the input impedance is
typically 5k. Using the buffered REFADJ input makes
buffering the external reference unnecessary; however,
the internal buffer output must be bypassed at REF with
a 1µF capacitor.
Connect REFADJ to AV
DD
to disable the internal buffer.
Directly drive REF using an external reference. During
conversion the external reference must be able to drive
100µA of DC load current and have an output imped-
ance of 10 or less. REFADJ’s impedance is typically
5k. The DC input impedance of REF is a minimum
40k.
For optimal performance, buffer the reference through
an op amp and bypass REF with a 1µF capacitor.
Consider the MAX1165/MAX1166s’ equivalent input
noise (38µV
RMS
) when choosing a reference.
Reading a Conversion Result
EOC is provided to flag the microprocessor when a con-
version is complete. The falling edge of EOC signals
that the data is valid and ready to be output to the bus.
D0–D15 are the parallel outputs of the MAX1165/
MAX1166. These three-state outputs allow for direct
connection to a microcontroller I/O bus. The outputs
remain high-impedance during acquisition and conver-
sion. Data is loaded onto the bus with the third falling
edge of CS with R/C high after t
DO
. Bringing CS high
forces the output bus back to high impedance. The
MAX1165/MAX1166 then wait for the next falling edge
of CS to start the next conversion cycle (Figure 2).
The MAX1165 loads the conversion result onto a 16-bit
wide data bus while the MAX1166 has a byte-wide out-
put format. HBEN toggles the output between the
most/least significant byte. The least significant byte is
loaded onto the output bus when HBEN is low and the
most significant byte is on the bus when HBEN is high
(Figure 2).
RESET
Toggle RESET with CS high. The next falling edge of CS
begins acquisition. This reset is an alternative to the
dummy conversion explained in the
Starting a Conversion
section.
Transfer Function
Figure 8 shows the MAX1165/MAX1166 output transfer
function. The output is coded in standard binary.
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy. If the input signal is multi-
plexed, the input channel should be switched immedi-
ately after acquisition, rather than near the end of or
after a conversion. This allows more time for the input
buffer amplifier to respond to a large step change in
input signal. The input amplifier must have a high
enough slew rate to complete the required output volt-
age change before the beginning of the acquisition
time. At the beginning of acquisition, the internal sam-
pling capacitor array connects to AIN (the amplifier out-
put), causing some output disturbance. Ensure that the
sampled voltage has settled to within the required limits
before the end of the acquisition time. If the frequency
of interest is low, AIN can be bypassed with a large
enough capacitor to charge the internal sampling
capacitor with very little ripple. However, for AC use,
AIN must be driven by a wideband buffer (at least
10MHz), which must be stable with the ADC’s capaci-
tive load (in parallel with any AIN bypass capacitor
used) and also settle quickly. An example of this circuit
using the MAX4434 is given in Figure 9.
MAX1165/MAX1166
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
______________________________________________________________________________________ 11
OUTPUT CODE
FULL-SCALE
TRANSITION
11...111
12 3
0
FS
INPUT VOLTAGE (LSB) FS - 3/2LSB
11...110
11...101
00...011
00...010
00...001
00...000
FS = V
REF
1 LSB = V
REF
65536
Figure 8. MAX1165/MAX1166 Transfer Function
MAX1165
MAX1166
MAX4434
ANALOG
INPUT
10
AIN
40pF
Figure 9. MAX1165/MAX1166 Fast Settling Input Buffer
MAX1165/MAX1166
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards. Do
not run analog and digital lines parallel to each other,
and do not lay out digital signal paths underneath the
ADC package. Use separate analog and digital ground
planes with only one point connecting the two ground
systems (analog and digital) as close to the device as
possible.
Route digital signals far away from sensitive analog and
reference inputs. If digital lines must cross analog lines,
do so at right angles to minimize coupling digital noise
onto the analog lines. If the analog and digital sections
share the same supply, then isolate the digital and ana-
log supply by connecting them with a low-value (10)
resistor or ferrite bead.
The ADC is sensitive to high-frequency noise on the
AV
DD
supply. Bypass AV
DD
to AGND with a 0.1µF
capacitor in parallel with a 1µF to 10µF low-ESR capaci-
tor with the smallest capacitor closest to the device.
Keep capacitor leads short to minimize stray inductance.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1165/MAX1166
are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of ±1 LSB guarantees no miss-
ing codes and a monotonic transfer function.
Aperture Jitter and Delay
Aperture jitter is the sample-to-sample variation in the
time between samples. Aperture delay is the time
between the rising edge of the sampling clock and the
instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s res-
olution (N bits):
SNR = (6.02
N + 1.76)dB
where N = 16 bits.
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
where V
1
is the fundamental amplitude and V
2
through
V
5
are the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the
RMS amplitude of the fundamental (maximum signal
component) to the RMS value of the next largest fre-
quency component.
THD
VVVV
V
+++
20
2
2
3
2
4
2
5
2
1
log
ENOB
SINAD
=
176
602
.
.
SINAD dB
Signal
Noise Distortion
RMS
RMS
( ) log
()
+
20
Low-Power, 16-Bit Analog-to-Digital Converter
with Parallel Interface
12 ______________________________________________________________________________________

MAX1165BCUI+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 16-Bit 165ksps 5.25V Precision ADC
Lifecycle:
New from this manufacturer.
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