LT1806/LT1807
16
18067fc
TYPICAL PERFORMANCE CHARACTERISTICS
40ns/DIV
0V
18067 G39
V
S
= p5V
FREQ = 1.92MHz
A
V
= 1
R
L
= 1k
±5V Large-Signal Response
20ns/DIV
18067 G40
0V
V
S
= p5V
FREQ = 4.48MHz
A
V
= 1
R
L
= 1k
±5V Small-Signal Response
20ns/DIV
18067 G41
0.5V
V
S
= 5V, 0V
FREQ = 5.29MHz
A
V
= 1
R
L
= 1k
5V Large-Signal Response
10ns/DIV
18067 G42
0V
V
S
= 5V, 0V
A
V
= 1
R
L
= 1k
5V Small-Signal Response
100ns/DIV
0V
0V
V
IN
1V/DIV
18067 G43
V
S
= 5V, 0V
A
V
= 2
R
L
= 1k
V
OUT
2V/DIV
Output Overdriven Recovery
20ns/DIV
18067 G44
0V
0V
V
SHDN
2V/DIV
V
S
= 5V, 0V
A
V
= 2
R
L
= 100Ω
V
OUT
2V/DIV
Shutdown Response
LT1806/LT1807
17
18067fc
Rail-to-Rail Characteristics
The LT1806/LT1807 have input and output signal range that
covers from negative power supply to positive power sup-
ply. Figure 1 depicts a simplifi ed schematic of the amplifi er.
The input stage is comprised of two differential amplifi ers,
a PNP stage Q1/Q2 and a NPN stage Q3/Q4 that are active
over different ranges of common mode input voltage. The
PNP differential pair is active between the negative supply
to approximately 1.5V below the positive supply. As the
input voltage moves closer toward the positive supply, the
transistor Q5 will steer the tail current I
1
to the current
mirror Q6/Q7, activating the NPN differential pair. The PNP
pair becomes inactive for the rest of the input common
mode range up to the positive supply.
APPLICATIONS INFORMATION
A pair of complementary common emitter stages Q14/Q15
that enable the output to swing from rail to rail constructs
the output stage. The capacitors C1 and C2 form the
local feedback loops that lower the output impedance at
high frequency. These devices are fabricated on Linear
Technologys proprietary high speed complementary
bipolar process.
Power Dissipation
The LT1806/LT1807 amplifi ers combine high speed with
large output current in a small package, so there is a need
to ensure that the die’s junction temperature does not
exceed 150°C. The LT1806 is housed in an SO-8 package
or a 6-lead SOT-23 package and the LT1807 is in an SO-8
Q4
Q6
Q3
Q7
Q10
Q1
Q13 Q15
OUT
Q2
Q11
Q12
Q9
Q5 V
BIAS
I
1
D2
D1
D5
D4
D3
D6
D7
D8
ESDD2ESDD1
+IN
–IN
V
ESDD3ESDD4
V
+
V
+
V
Q8
R2R1
R3 R4 R5
Q14
18067 F01
+
I
2
C2
C
C
V
+
C1
BUFFER
AND
OUTPUT BIAS
Q17
Q16
ESDD5
SHDN
V
+
V
R7
100k
R6
40k
D9
V
+
V
ESDD6
BIAS
GENERATION
Figure 1. LT1806 Simplifi ed Schematic Diagram
LT1806/LT1807
18
18067fc
or 8-lead MSOP package. All packages have the V
sup-
ply pin fused to the lead frame to enhance the thermal
conductance when connecting to a ground plane or a
large metal trace. Metal trace and plated through-holes
can be used to spread the heat generated by the device
to the backside of the PC board. For example, on a 3/32"
FR-4 board with 2oz copper, a total of 660 square mil-
limeters connects to Pin 4 of LT1807 in an SO-8 package
(330 square millimeters on each side of the PC board) will
bring the thermal resistance, θ
JA
, to about 85°C/W. Without
extra metal trace beside the power line connecting to the
V
pin to provide a heat sink, the thermal resistance will be
around 105°C/W. More information on thermal resistance
for all packages with various metal areas connecting to
the V
pin is provided in Tables 1, 2 and 3.
Table 1. LT1806 6-Lead SOT-23 Package
COPPER AREA
BOARD AREA
(mm
2
)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
TOPSIDE (mm
2
)
270 2500 135°C/W
100 2500 145°C/W
20 2500 160°C/W
0 2500 200°C/W
Device is mounted on topside.
Table 2. LT1806/LT1807 SO-8 Package
COPPER AREA
BOARD AREA
(mm
2
)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
TOPSIDE
(mm
2
)
BACKSIDE
(mm
2
)
1100 1100 2500 65°C/W
330 330 2500 85°C/W
35 35 2500 95°C/W
35 0 2500 100°C/W
0 0 2500 105°C/W
Device is mounted on topside.
APPLICATIONS INFORMATION
Table 3. LT1807 8-Lead MSOP Package
COPPER AREA
BOARD AREA
(mm
2
)
THERMAL RESISTANCE
(JUNCTION-TO-AMBIENT)
TOPSIDE
(mm
2
)
BACKSIDE
(mm
2
)
540 540 2500 110°C/W
100 100 2500 120°C/W
100 0 2500 130°C/W
30 0 2500 135°C/W
0 0 2500 140°C/W
Device is mounted on topside.
Junction temperature T
J
is calculated from the ambient
temperature T
A
and power dissipation P
D
as follows:
T
J
= T
A
+ (P
D
θ
JA
)
The power dissipation in the IC is the function of the supply
voltage, output voltage and the load resistance. For a given
supply voltage, the worst-case power dissipation P
D(MAX)
occurs at the maximum quiescent supply current and at
the output voltage which is half of either supply voltage
(or the maximum swing if it is less than 1/2 the supply
voltage). P
D(MAX)
is given by:
P
D(MAX)
= (V
S
• I
S(MAX)
) + (V
S
/2)2/R
L
Example: An LT1807 in SO-8 mounted on a 2500mm
2
area of PC board without any extra heat spreading plane
connected to its V
pin has a thermal resistance of
105°C/W, θ
JA
. Operating on ±5V supplies with both ampli-
ers simultaneously driving 50Ω loads, the worst-case
power dissipation is given by:
P
D(MAX)
= 2 • (10 • 14mA) + 2 • (2.5)
2
/50
= 0.28 + 0.25 = 0.53W

LT1807IS8#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Precision Amplifiers 325MHz, 2x, R2R In & Out, L Dist, L N P
Lifecycle:
New from this manufacturer.
Delivery:
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