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MC74ACT564DWR2G

P1-P3P4-P6P7-P7
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 4
1 Publication Order Number:
MC74ACT564/D
MC74ACT564
Octal D-Type Flip-Flop
with 3-State Outputs
The MC74ACT564 is a high−speed, low power octal flip−flop with
a buffered common Clock (CP) and a buffered common Output
Enable (OE
).
The information presented to the D inputs is stored in the flip−flops
on the LOW−to−HIGH Clock (CP) transition.
The MC74ACT564 device is functionally indentical to the
MC74ACT574, but with inverted outputs.
Features
• Inputs and Outputs on the Opposite Sides of the Package Allowing
Easy Interface with Microprocessors
• Useful as Input or Output Port for Microprocessor
• Functionally Indentical to the MC74ACT574 but with Inverted
Outputs
• 3−State Outputs for Bus−Oriented Applications
• Outputs Source/Sink 24 mA
• TTL Compatible Inputs
• These are Pb−Free Devices
1920 18 17 16 15 14
21 34567
V
CC
13
8
12
9
11
10
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
CP
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
Figure 1. Pinout: 20−Lead Packages Conductors
(Top View)
PIN ASSIGNMENT
PIN
D
0
−D
7
FUNCTION
Data Inputs
CP Clock Pulse Input
OE 3−State Output Enable Input
O
0
−O
7
3−State Outputs
Figure 2. Logic Symbol
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
OE
See general marking information in the device marking
section on page 5 of this data sheet.
DEVICE MARKING INFORMATION
www.onsemi.com
SOIC−20W
DW SUFFIX
CASE 751D
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
MC74ACT564
www.onsemi.com
2
Figure 3. Logic Diagram
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CD
Q
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
OE
CP
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
CD
Q
Please note that this diagram is provided only for the understanding of
logic operations and should not be used to estimate propagation delays.
FUNCTION TABLE
Inputs Internal Outputs
Function
OE CP D Q O
H H L NC Z Hold
H HH NC Z Hold
H LH Z Load
H HL Z Load
L LH H Data Available
L HL L Data Available
L HL NC NC No Change in Data
L H H NC NC No Change in Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW−to−HIGH Transition
NC = No Change
FUNCTIONAL DESCRIPTION
The MC74ACT564 consists of eight edge−triggered
flip−flops with individual D−type inputs and 3−state
complementary outputs. The buffered clock and buffered
Output Enable are common to all flip−flops. The eight
flip−flops will store the state of their individual D inputs that
meet the setup and hold times requirements on the
LOW−to−HIGH Clock (CP) transition. With the Output
Enable (OE
) LOW, the contents of the eight flip−flops are
available at the outputs. When OE
is HIGH, the outputs go
to the high impedance state. Operation of the OE
input does
not affect the state of the flip−flops.
MC74ACT564
www.onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V
V
IN
DC Input Voltage (Referenced to GND) −0.5 to V
CC
+0.5 V
V
OUT
DC Output Voltage (Referenced to GND) (Note 1) −0.5 to V
CC
+0.5 V
I
IK
DC Input Diode Current ±20 mA
I
OK
DC Output Diode Current ±50 mA
I
OUT
DC Output Sink/Source Current ±50 mA
I
CC
DC Supply Current, per Output Pin ±50 mA
I
GND
DC Ground Current, per Output Pin ±100 mA
T
STG
Storage Temperature Range *65 to )150
_C
T
L
Lead temperature, 1 mm from Case for 10 Seconds 260
_C
T
J
Junction Temperature Under Bias 140
_C
q
JA
Thermal Resistance (Note 2) 65.8
_C/W
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 2000
> 200
> 1000
V
I
Latchup
Latchup Performance Above V
CC
and Below GND at 85_C (Note 6)
±100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
OUT
absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD 51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
V
CC
DC Input Voltage (Referenced to GND) 4.5 5.5 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types −40 25 +85 °C
t
r
, t
f
Input Rise and Fall Time (Note 8) V
CC
= 4.5 V
V
CC
= 5.5 V
0
0
10
8.0
10
8.0
ns/V
I
OH
Output Current − High −24 mA
I
OL
Output Current − Low 24 mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. Unused Inputs may not be left open. All inputs must be tied to a high voltage level or low logic voltage level.
8. V
in
from 0.8 V to 2.0 V; refer to individual Data Sheets for devices that differ from the typical input rise and fall times.
P1-P3P4-P6P7-P7

MC74ACT564DWR2G

Mfr. #:
Buy MC74ACT564DWR2G
Manufacturer:
ON Semiconductor
Description:
Flip Flops 5V Octal D-Type w/3 State Outupts
Lifecycle:
New from this manufacturer.
Delivery:
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