LTC2919CDDB-3.3#TRPBF

LTC2919
7
2919f
BLOCK DIAGRA
W
+
+
+
ADJUSTABLE
PULSE
GENERATOR
THREE-STATE
DECODE
THREE-STATE
DECODE
TMR
RST
OUT1
OUT2
GND
2919 BD
200ms
PULSE
GENERATOR
+
SEL
CONTROL 1CONTROL 2
EN
ADJ1
ADJ2
REF
V
CC
V
CC
6.5V
+
500mV
+
1.000V
V
CC
SEL
GND
OPEN
V
CC
CONTROL 1
H
L
L
CONTROL 2
H
H
L
CONTROL = H = NEGATIVE POLARITY
CONTROL = L = POSITIVE POLARITY
TI I G DIAGRA S
WWU
2919 TD
1V
1V
V
CC(UVLO)
V
CC(UVLO)
+ ΔV
CC(UVLO)
t
PROP
t
PROP
V
CC
OUT
t
UV
t
RST
RST
UVLO Timing
1V
V
RT
V
RT
ΔV
RT
V
ADJ
t
PROP
t
RST
RST
Negative Polarity Input Timing
1V
t
PROP
t
PROP
OUT
V
ADJ
t
PROP
1V
V
RT
t
RST
RST
Positive Polarity Input Timing
V
RT
+ ΔV
RT
1V
t
PROP
t
PROP
OUT
NOTES:
1. ΔV
RT
AND ΔV
CC(UVLO)
= 0, except in
Comparator Mode
2. IN COMPARATOR MODE, t
RST
= t
PROP
.
PI FU CTIO S
UUU
(MSOP/DFN Package)
ADJ1 (Pin 10): Adjustable Voltage Input 1. Input to volt-
age monitor comparator 1 (0.5V nominal threshold). The
polarity of the input is selected by the state of the SEL
pin (refer to Table 1). Tie to REF if unused (with SEL =
V
CC
or Open).
Exposed Pad (Pin 11, DFN Only): The Exposed Pad may
be left unconnected. For better thermal contact, tie to a PCB
trace. This trace must be grounded or unconnected.
LTC2919
8
2919f
APPLICATIO S I FOR ATIO
WUU
U
The LTC2919 is a low power, high accuracy triple/dual
supply monitor with two adjustable inputs and an accurate
UVLO that can monitor a third supply. Reset timeout may
be selected with an external capacitor, set to an internally
generated 200ms, or disabled entirely.
The three-state polarity select pin (SEL) chooses one of
three possible polarity combinations for the adjustable
input thresholds, as described in Table 1. An individual
output is released when its corresponding ADJ input is
valid (above threshold if confi gured for positive polarity,
below threshold if confi gured for negative polarity).
Both input voltages (V
ADJ1
and V
ADJ2
) must be valid and
V
CC
above the UVLO threshold for longer than the reset
timeout period before RST is released. The LTC2919 as-
serts the reset output during power-up, power-down and
brownout conditions on any of the voltage inputs.
Power-Up
The LTC2919 uses proprietary low voltage drive circuitry
for the RST, OUT1 and OUT2 pins which holds them low
with V
CC
as low as 200mV. This helps prevent indeter-
minate voltages from appearing on the outputs during
power-up.
In applications where the low voltage pull-down capabil-
ity is important, the supply to which the external pull-up
resistor connects should be the same supply which pow-
ers the part. Using the same supply for both ensures that
RST, OUT1 and OUT2 never fl oat above 200mV during
power-up, as the pull-down ability of the pin will then
increase as the required pull-down current to maintain a
logic low increases.
Once V
CC
passes the UVLO threshold, polarity selection and
timer initialization will occur. If the monitored ADJ input is
valid, the corresponding OUT will be released. When both
ADJ1 and ADJ2 are valid, the appropriate timeout delay
will begin, after which RST will be released.
Power-Down
On power-down, once V
CC
drops below the UVLO threshold
or either V
ADJ
becomes invalid, RST asserts logic low. V
CC
of at least 0.5V guarantees a logic low of 0.15V at RST.
Shunt Regulator
The LTC2919 contains an internal 6.5V shunt regulator on
the V
CC
pin to allow operation from a high voltage supply.
To operate the part from a supply higher than 6V, the V
CC
pin must have a current-limiting series resistor, R
CC
, to
the supply. This resistor should be sized according to the
following equation:
V
S(MAX)
6.2V
10mA
R
CC
V
S(MIN)
6.8V
200µA + I
REF
where V
S(MIN)
and V
S(MAX)
are the operating minimum and
maximum of the supply, and I
REF
is the maximum current
the user expects to draw from the reference output.
As an example, consider operation from an automobile bat-
tery which might dip as low as 10V or spike to 60V. Assume
that the user will be drawing 100A from the reference. We
must then pick a resistance between 5.4k and 10.7k.
When the V
CC
pin is connected to a low impedance supply,
it is important that the supply voltage never exceed 6V,
or the shunt regulator may begin to draw large currents.
Some supplies may have a nominal value suffi ciently
close to the shunt regulation voltage to prevent sizing of
the resistor according to the above equation. For such
supplies, a 470 series resistor may be used.
Adjust Polarity Selection
The external connection of the SEL pin selects the polarities
of the LTC2919 adjustable inputs. SEL may be connected
to GND, connected to V
CC
or left unconnected during
normal operation. When left unconnected, the maximum
leakage allowable from the pin is ±5µA. Table 1 shows
the three possible selections of polarity based on SEL
connection.
Table 1. Voltage Threshold Selection
ADJ1 INPUT ADJ2 INPUT SEL
Positive Polarity
(+) UV or (–) OV
Positive Polarity
(+) UV or (–) OV
V
CC
Positive Polarity
(+) UV or (–) OV
Negative Polarity
(–) UV or (+) OV
Open
Negative Polarity
(–) UV or (+) OV
Negative Polarity
(–) UV or (+) OV
Ground
Note: Open = open circuit or driven by a three-state buffer in high impedance
state with leakage current less than 5A.
LTC2919
9
2919f
If the users application requires, the SEL pin may be driven
using a three-state buffer which satisfi es the V
IL
, V
IH
and
leakage conditions of this three-state input pin.
If the state of the SEL pin confi gures a given input as
“negative polarity,” the voltage at that ADJ pin must be
below the trip point (0.5V nominal), or the corresponding
OUT and RST output will be pulled low. Conversely, if a
given input is confi gured as “positive polarity”, the ADJ pin
voltage must be above the trip point or the corresponding
OUT and RST will assert low.
Thus, a “negative polarity” input may be used to deter-
mine whether a monitored negative voltage is smaller in
absolute value than it should be (–UV), or a monitored
positive voltage is larger than it should be (+OV). The
APPLICATIO S I FOR ATIO
WUU
U
opposite is true for a “positive polarity” input (–OV or
+UV). These polarity defi nitions are also shown in Table
1. For purposes of this data sheet, a negative voltage is
considered “undervoltage” if it is closer to ground than it
should be (e.g., –4.3V for a –5V supply).
Proper confi guration of the SEL pin and setting of the
trip-points via external resistors allows for any two fault
conditions to be detected. For example, the LTC2919 may
monitor two supplies (positive, negative or one of each)
for UV or for OV (or one UV and one OV). It may also
monitor a single supply (positive or negative) for both UV
and OV. Tables 2a and 2b show example confi gurations
for monitoring possible combinations of fault condition
and supply polarity.
ADJ1
ADJ2
OUT1
OUT2
SEL
5V15V
R
P2B
115k
R
P1B
13.7k
R
P1A
11.5k
R
P2A
309k
REF
SEL = V
CC
2 Positive UV
ADJ1
ADJ2
OUT1
OUT2
SEL
5V15V
R
P2B
133k
R
P1B
13.7k
R
P1A
20k
R
P2A
619k
REF
2 Positive OV
ADJ1
ADJ2
OUT1
OUT2
SEL
–5V–15V
R
N2B
137k
R
N1B
13.3k
R
N1A
10.7k
R
N2A
309k
REF
2 Negative UV
SEL = GND
ADJ1
ADJ2
OUT1
OUT2
SEL
–5V–15V
R
N2B
137k
R
N1B
11.8k
R
N1A
30.9k
R
N2A
1.02M
REF
2 Negative OV
ADJ1
ADJ2
OUT1
OUT2
SEL
–15V15V
R
N2
1.02M
R
N1
30.9k
R
P1
11.5k
R
P2
309k
REF
1 Positive UV, 1 Negative OV
ADJ1
ADJ2
OUT1
OUT2
OV (15V)
UV (–15V)
OV (15V)
0V (5V)
UV (–15V)
UV (–5V)
UV (15V)
UV (5V)
OV (–15V)
OV (–5V)
UV (15V)
OV (–15V)
SEL
–15V15V
R
N2
309k
R
N1
10.7k
R
P1
20k
R
P2
619k
REF
1 Positive OV, 1 Negative UV
Table 2a. Possible Combinations of Supply Monitoring. For Example Purposes, All Supplies are Monitored at 5% Tolerance and
Connections are Shown Only for ADJ1, ADJ2, REF, SEL, OUT1 and OUT2. Output Pull-up Resistors are Omitted for Clarity.

LTC2919CDDB-3.3#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Supervisory Circuits Dual Supply Monitor with Selectable Polarity, Independent Monitor Outputs
Lifecycle:
New from this manufacturer.
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