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ISL1561IRZ

P1-P3P4-P6P7-P9P10-P12P13-P13
ISL1561
10
FN7941.1
February 26, 2013
General Description
The ISL1561 is a class G amplifier designed to reduce power
consumption in ADSL2+ and VDSL2 applications compared to
class AB. With the high PAR used for xDSL signals, a supply
voltage of +14V can be used for the majority of the small
amplitude cycles while boosting to a supply voltage of +28V can
be used for the few high amplitude cycles.
Digital Interface
A 12-bit serial port interface is used to program ISL1561. The
first bit defines the write (1’b1) and read (1’b0) operation to the
register. The following 3-bit calls the registers. The last 8-bit
programs the registers. Default start-up for ISL1561 is in disable
mode with boost and CS pins having internal pull ups and SCLK
and SDATA pins having internal pull downs. ISL1561 can only be
programmed through the SPI when CS is set low.
Register Listing
ADDRESS FUNCTION BIT DESCRIPTION
3’h3 Setting of quiescent current of port AB [7] Boost disable
[6:0] Program quiescent current of port AB.
3’h7 Setting of quiescent current of port CD [7] Boost disable
[6:0] Program quiescent current of port CD.
FIGURE 27. 12 BITS SERIAL ADDRESSING DIAGRAM
FIGURE 28. 12 BITS SERIAL ADDRESSING DIAGRAM
CS
1230
Z-HI
Z-HI
SCLK
SDATA
D[0]
ADDR[0:2]
CURRENT SETTING VALUE
D[1] D[2]
D[3] D[4]
D[5]
D[6] D[7]
W/R
BN B(N-1) B(N-2) B1 B0
SCLK
SDATA
LSB MSB
t
t
SD
t
HD
tt
r
t
w
LOAD LSB FIRST, MSB LAST
t
f
CS
t
SC
t
HC
t
SC
ISL1561
11
FN7941.1
February 26, 2013
Boost Control
Table 2 summarizes the logic of register MSB on boost operations followed by Figure 29 with the recommended look ahead timing for
the boost signal.
TABLE 1. SERIAL TIMING DIAGRAM
PARAMETER RECOMMENDED OPERATING RANGE DESCRIPTION
t ≥100ns Clock Period
t
r
/t
f
0.05*t Clock Rise/Clock Fall
t
HC
≥7ns Data Hold Time
t
SD
≥10ns Data Setup Time
t
HC
≥2.8ns CS Hold Time
t
SC
≥0.5ns CS Setup Time
t
W
0.50*t Clock Pulse Width
TABLE 2. REGISTER MSB ON BOOST OPERATION
Reg3 8’h[7] Reg7 8’h[7] BOOST PIN BOOST OPERATION
0X 1 1
X0 1 1
11 X 0
XX 0 0
NOTE: X = do not care
FIGURE 29. SERIAL TIMING DIAGRAM
TABLE 3. EXTERNAL BOOST SIGNAL TIMING PARAMETERS
PARAMETER RECOMMENDED OPERATING RANGE DESCRIPTION
t
d
100ns Look ahead boost
ISL1561
12
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN7941.1
February 26, 2013
For additional products, see www.intersil.com/product_tree
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure,
personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of
our winning team, visit our website and career page at www.intersil.com
.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page.
Also, please check the product information page to ensure that you have the most updated datasheet: ISL1561
To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff
Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest revision.
DATE REVISION CHANGE
January 24, 2013 FN7941.1 Changed MIN/MAX specs for “Differential Output Offset Voltage” on page 5 from -75/75mV to -125/125mV.
November 21, 2012 Added resistor values to Figure 3 on page 3.
Edited table heading for columns 1 and 2 in Table 2 on page 11.
October 5, 2012 FN7941.0 Initial Release.
P1-P3P4-P6P7-P9P10-P12P13-P13

ISL1561IRZ

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Buffers & Line Drivers Fixed Gain Dual Port Class-G+ Differenti
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