Typical Operating Characteristics
(V+ = +5V, T
A
= +25°C, unless otherwise noted.)
MAX4548/MAX4549
Serially Controlled, Triple 3x2 Audio/Video
Crosspoint Switches
6 _______________________________________________________________________________________
Note 2: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 3: Guaranteed by design. Not subject to production testing.
Note 4: ∆R
ON
= R
ON(MAX)
- R
ON(MIN)
.
Note 5: Resistance flatness is defined as the difference between the maximum and minimum on-resistance values, as measured
over the specified analog signal range.
Note 6: Leakage parameters are 100% tested at maximum rated temperature and guaranteed by correlation at T
A
= +25°C.
Note 7: Off-isolation = 20log (V
COM
_ / V
NO
_ _ ), V
COM
_ = output, V
NO
_ _ = input to off switch.
Note 8: All timing is measured from the clock’s falling edge preceding the ACK signal for 2-wire and from the rising edge of CS for
3-wire. Turn-off time is defined at the output of the switch for a 0.5V change, tested with a 300Ω load to ground. Turn-on
time is defined at the output of the switch for a 0.5V change and measured with a 5kΩ load resistor to GND. All timing is
shown with respect to 20% V+ and 70% V+, unless otherwise noted.
Note 9: Supply current can be as high as 2mA per switch during switch transitions in the clickless mode, corresponding to a 48mA
total supply transient current requirement.
Note 10: Leakage testing is guaranteed by testing with a +5.25V supply.
Note 11: C
b
= capacitance of one bus line in pF. Tested with C
b
= 400pF.
Note 12: Typical values are for MAX4548 devices.
3-WIRE TIMING CHARACTERISTICS (Figure 5)
(V+ = +2.7V to +5.25V, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
SCLK Pulse Width Low t
CL
200
V+ = 2.7V to 5.25V 0 2.1
ns
Fall Time (SCLK, DIN, CS)
t
F
2 µs
SCLK Pulse Width High t
CH
200 ns
CS to SCLK Rise Hold
t
CSH
0 ns
Rise Time (SCLK, DIN, CS)
t
R
DIN to SCLK Setup t
DS
100 ns
Operating Frequency f
OP
V+ = 4.75V to 5.25V 010
MHz
DIN to SCLK Hold t
DH
0 ns
2 µs
CS to SCLK Rise Setup
t
CSS
100 ns
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCLK Fall to Output Data Valid t
DO
C
LOAD
= 50pF 200 ns
CS Pulse Width High
t
CSW
40 ns
