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TEA1751T/N1,518

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31
TEA1751T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 10 January 2013 19 of 31
NXP Semiconductors
TEA1751T
HV start-up flyback controller with integrated PFC controller
Accurate OVP detection is made possible by adjusting the value of R
FBAUX
to the turns
ratio of the transformer.
7.3.9 Overcurrent protection (FBSENSE pin)
The primary peak current in the transformer is measured accurately cycle-by-cycle using
the external sense resistor R
sense2
. V
FBCTRL
sets the level to which the OCP circuit limits
V
FBSENSE
(see Section 7.3.3). The OCP detection is suppressed during the leading-edge
blanking period, t
leb
, to prevent false triggering due to switch-on spikes.
7.3.10 Overpower protection
During the primary stroke of the flyback converter, the input voltage is measured by
sensing the current drawn from the FBAUX pin.
The current information is used to adjust the peak drain current of the flyback converter,
measured from the FBSENSE pin. The internal compensation is such, that a maximum
output power is realized which is almost independent of the input voltage.
The OPP curve is given in Figure 15
.
7.3.11 Driver (FBDRIVER pin)
The driver circuit to the power MOSFET gate has a current sourcing capability of 500 mA
and a current sink capability of 1.2 A. These capabilities permit fast turn-on and turn-off of
the power MOSFET, thus ensuring efficient operation.
Fig 14. OCP leading-edge blanking
t
leb
OCP level
V
FBSENSE
t
014aaa022
Fig 15. Overpower protection curve
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TEA1751T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 10 January 2013 20 of 31
NXP Semiconductors
TEA1751T
HV start-up flyback controller with integrated PFC controller
8. Limiting values
[1] Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
Voltages
V
CC
supply voltage 0.4 +38 V
V
LATCH
voltage on the LATCH pin current limited 0.4 +5 V
V
FBCTRL
voltage on the FBCTRL pin 0.4 +5 V
V
PFCCOMP
voltage on the PFCCOMP
pin
0.4 +5 V
V
VINSENSE
voltage on the VINSENSE
pin
0.4 +5 V
V
VOSENSE
voltage on the VOSENSE
pin
0.4 +5 V
V
PFCAUX
voltage on the PFCAUX pin 25 +25 V
V
FBSENSE
voltage on the FBSENSE pin current limited 0.4 +5 V
V
PFCSENSE
voltage on the PFCSENSE
pin
current limited 0.4 +5 V
V
HV
voltage on the HV pin 0.4 +650 V
Currents
I
FBCTRL
current on the FBCTRL pin 30 mA
I
FBAUX
current on the FBAUX pin 1+1mA
I
PFCSENSE
current on the PFCSENSE
pin
1+10mA
I
FBSENSE
current on the FBSENSE pin 1+10mA
I
FBDRIVER
current on the FBDRIVER
pin
duty cycle < 10 % 0.8 +2 A
I
PFCDRIVER
current on the PFCDRIVER
pin
duty cycle < 10 % 0.8 +2 A
I
HV
current on the HV pin - 8 mA
General
P
tot
total power dissipation T
amb
<75C-0.6W
T
stg
storage temperature 55 +150 C
T
j
junction temperature 40 +150 C
ESD
V
ESD
electrostatic discharge
voltage
class 1
human body
model
pins 1 to 13
[1]
-2000V
pin 16 (HV)
[1]
-1500V
machine model
[2]
-200V
charged device
model
-500V
TEA1751T All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 10 January 2013 21 of 31
NXP Semiconductors
TEA1751T
HV start-up flyback controller with integrated PFC controller
[2] Equivalent to discharging a 200 pF capacitor through a 0.75 H coil and a 10 resistor.
9. Thermal characteristics
10. Characteristics
Table 4. Thermal characteristics
Symbol Parameter Conditions Typ Unit
R
th(j-a)
thermal resistance from
junction to ambient
in free air; JEDEC test board 124 K/W
R
th(j-c)
thermal resistance from
junction to case
in free air; JEDEC test board 37 K/W
Table 5. Characteristics
T
amb
=25
C; V
CC
= 20 V; all voltages are measured with respect to ground; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Start-up current source (HV pin)
I
HV
current on the HV pin V
HV
>80V
V
CC
<V
trip
;
V
th(UVLO)
<V
CC
<V
startup
-1.0-mA
V
trip
<V
CC
<V
th(UVLO)
-5.4-mA
with auxiliary supply 8 20 40 A
V
BR
breakdown voltage 650 - - V
Supply voltage management (V
CC
pin)
V
trip
trip voltage 0.55 0.65 0.75 V
V
startup
start-up voltage 212223V
V
th(UVLO)
undervoltage lockout threshold
voltage
14 15 16 V
V
start(hys)
hysteresis of start voltage during start-up phase - 300 - mV
V
hys
hysteresis voltage V
startup
V
th(UVLO)
6.3 7 7.7 V
I
ch(low)
low charging current V
HV
>80V; V
CC
<V
trip
or
V
th(UVLO)
<V
CC
<V
startup
1.2 1.0 0.8 mA
I
ch(high)
high charging current V
HV
>80V; V
trip
<V
CC
< V
th(UVLO)
4.6 5.4 6.3 mA
I
CC(oper)
operating supply current no-load on the FBDRIVER and
PFCDRIVER pins
2.25 3 3.75 mA
Input Voltage Sensing PFC (VINSENSE pin)
V
stop(VINSENSE)
stop voltage on the VINSENSE
pin
0.86 0.89 0.92 V
V
start(VINSENSE)
start voltage on the VINSENSE
pin
1.11 1.15 1.19 V
V
pu(VINSENSE)
pull-up voltage difference on
the VINSENSE pin
active after V
stop(VINSENSE)
is
detected
-100-mV
I
pu(VINSENSE)
pull-up current on the
VINSENSE pin
active after V
stop(VINSENSE)
is
detected
55 47 40 A
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P31

TEA1751T/N1,518

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Manufacturer:
NXP Semiconductors
Description:
AC/DC Converters GRNCHIP III PRIMARY
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