QorIQ P5040
Development System
QorIQ Multicore Processor Development
Overview
The P5040DS-PA is a flexible development
system based on the dual-core 32/64-bit
moded P5040 device. The board, with
its 2.2 GHz P5040 and rich I/O mix, is
intended for evaluation of the QorIQ P5040/
P5021processor in networking, telecom
and industrial applications, where its high-
performance, high-efficiency core and
integration make it very well suited as a
control plane processor.
The P5040 development system, which
exercises most capabilities of the P5040
processor, can serve as a reference for the
customer’s own hardware development, as a
debug tool to check behaviors on the board
compared to behaviors seen on customer
boards or be used for software development
and performance evaluation prior to
completion of the customer’s own board.
The P5040/P5021 processor is based
upon the e5500mc core, built on Power
Architecture
®
, offering speeds of 1.8 to 2.4
GHz. It has a three-level cache hierarchy with
32 KB of instruction and data cache per core,
512 KB of unified backside L2 cache per
core, and 2 MB of shared frontside CoreNet
platform cache fronting the dual memory
controllers. The processor’s I/O includes
20 SerDes lanes running at up to 5 GHz,
multiplexed across three PCI Express
®
gen.
2.0 controllers, two 10 GE XAUI interfaces,
four 1 GbE SGMII interfaces, four 2.5 Gb/s
SGMII interfaces, two SATA 2.0 interfaces and
the high-speed Aurora debug interface. It has
a 64-bit DDR3 and DDR3L (low power) DRAM
interface with 8-bit ECC support running at up
to 1600 MHz data rate. It includes two USB
2.0 interfaces (including PHY), two DUARTs,
an SD/MMC interface, a 32-bit local bus, four
I
2
C and SPI. It also includes the accelerator
blocks collectively known as the data path
acceleration architecture (DPAA) that offload
various tasks from the core, including routine
packet handling and security algorithm
calculation as well as support for RAID 5/6
hardware assist.
The P5040DS has significant flexibility in
allocation of its 20 SerDes lanes to various
functions. Its base configuration supports two
RGMII ports, two PCI Express x2 slots (two
lanes to each slot), 4 x 4 slots for the optional
Freescale SGMII-PEX-RISER, a 2 x 4 slot
for the optional Freescale XAUI-RISER, the
Aurora high-speed debug port and two SATA
ports. It can also be configured to support
one PCI Express slot of widths up to x8.
