64K/128K x 8/9
Dual-Port Static RAM
CY7C008/009
CY7C018/019
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
Document #: 38-06041 Rev. *A Revised April 8, 2002
25/0251
Features
True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
64K x 8 organization (CY7C008)
128K x 8 organization (CY7C009)
64K x 9 organization (CY7C018)
128K x 9 organization (CY7C019)
0.35-micron CMOS for optimum speed/power
High-speed access: 12
[1]
/15/20 ns
Low operating power
Active: I
CC
= 180 mA (typical)
Standby: I
SB3
= 0.05 mA (typical)
Fully asynchronous operation
Automatic power-down
Expandable data bus to 16/18 bits or more using Mas-
ter/Slave chip select when using more than one device
On-chip arbitration logic
Semaphores included to permit software handshaking
between ports
INT
flags for port-to-port communication
Dual Chip Enables
Pin select for Master or Slave
Commercial and Industrial temperature ranges
Available in 100-pin TQFP
Pin-compatible and functionally equivalent to IDT7008
Notes:
1. See page 6 for Load Conditions.
2. I/O
0
I/O
7
for x8 devices; I/O
0
I/O
8
for x9 devices.
3. A
0
A
15
for 64K devices; A
0
A
16
for 128K.
4. BUSY
is an output in master mode and an input in slave mode.
I/O
Control
Address
Decode
A
0L
A
15/16L
CE
L
OE
L
R/W
L
BUSY
L
I/O
Control
Interrupt
Semaphore
Arbitration
SEM
L
INT
L
M/S
Logic Block Diagram
A
0L
A
15/16L
True Dual-Ported
RAM Array
A
0R
A
15/16R
CE
R
OE
R
R/W
R
BUSY
R
SEM
R
INT
R
Address
Decode
A
0R
A
15/16R
[2]
[2]
[3]
[3]
[4]
[4]
[3] [3]
R/W
L
CE
0L
CE
1L
OE
L
I/O
0L
I/O
7/8L
CE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0R
I/O
7/8R
CE
R
16/17
8/9
16/17
8/9
16/17 16/17
CY7C008/009
CY7C018/019
Document #: 38-06041 Rev. *A Page 2 of 19
Functional Description
The CY7C008/009 and CY7C018/019 are low-power CMOS
64K, 128K x 8/9 dual-port static RAMs. Various arbitration
schemes are included on the devices to handle situations
when multiple processors access the same piece of data. Two
ports are provided permitting independent, asynchronous ac-
cess for reads and writes to any location in memory. The de-
vices can be utilized as standalone 8/9-bit dual-port static
RAMs or multiple devices can be combined in order to function
as a 16/18-bit or wider master/slave dual-port static RAM. An
M/S
pin is provided for implementing 16/18-bit or wider mem-
ory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communica-
tions status buffering, and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE
),
read or write enable (R/W
), and output enable (OE). Two flags are
provided on each port (BUSY and INT). BUSY signals that the port is
trying to access the same location currently being accessed by the
other port. The interrupt flag (INT
) permits communication between
ports or systems by means of a mail box. The semaphores are used
to pass a flag, or token, from one port to the other to indicate that a
shared resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared resource is
in use. An automatic power-down feature is controlled independently
on each port by a chip select (CE
) pin.
The CY7C008/009 and CY7C018/019 are available in 100-pin
Thin Quad Plastic Flatpack (TQFP) packages.
Pin Configurations
Note:
5. This pin is NC for CY7C008.
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
NC
NC
A7R
A8R
A9R
A10R
A15R
A12R
A14R
GND
NC
NC
CE0R
A13R
A11R
NC
NC
CE1R
SEMR
R/WR
OER
GND
GND
NC
A16R
58
57
56
55
54
53
52
51
CY7C008 (64K x 8)
NC
NC
A7L
A8L
A9L
A10L
A15L
A12L
A14L
VCC
NC
NC
CE0L
A13L
A11L
NC
NC
CE1L
SEML
R/WL
OEL
GND
NC
NC
A16L
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
NC
NC
A6L
A5L
A4L
A3L
INTL
A1L
NC
GND
M/S
A0R
A1R
A0L
A2L
BUSYR
INTR
A2R
A3R
A4R
A5R
A6R
NC
NC
BUSYL
34 35 36 424139 403837 43 44 45 5048 494746
NC
NC
NC
I/O7R
I/O6R
I/O5R
I/01R
I/O3R
I/O2R
GND
VCC
GND
I/O2L
VCC
I/O4R
I/O0L
I/O1L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
NC
GND
I/O0R
3332313029282726
CY7C009 (128K x 8)
100-Pin TQFP
(Top View)
[5]
[5]
CY7C008/009
CY7C018/019
Document #: 38-06041 Rev. *A Page 3 of 19
Pin Configurations (continued)
Note:
6. This pin is NC for CY7C018.
Selection Guide
CY7C008/009
CY7C018/019
-12
[1]
CY7C008/009
CY7C018/019
-15
CY7C008/009
CY7C018/019
-20
Maximum Access Time (ns) 12 15 20
Typical Operating Current (mA) 195 190 180
Typical Standby Current for I
SB1
(mA) (Both ports TTL level) 55 50 45
Typical Standby Current for I
SB3
(mA) (Both ports CMOS level) 0.05 0.05 0.05
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
NC
NC
A7R
A8R
A9R
A10R
A15R
A12R
A14R
GND
NC
NC
CE0R
A13R
A11R
NC
NC
CE1R
SEM
R
R/W
R
OE
R
GND
GND
NC
A16R
58
57
56
55
54
53
52
51
CY7C018 (64K x 9)
NC
NC
A7L
A8L
A9L
A10L
A15L
A12L
A14L
VCC
NC
NC
CE
0L
A13L
A11L
NC
NC
CE1L
SEML
R/WL
OEL
GND
NC
NC
A16L
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
NC
NC
A6L
A5L
A4L
A3L
BUSYL
A1L
INTL
GND
VCC
INTR
A0R
A0L
A2L
M/S
BUSYR
A1R
A2R
A3R
A4R
A5R
A6R
NC
GND
34 35 36 424139 403837 43 44 45 5048 494746
NC
NC
I/O8R
I/O7R
I/O6R
I/O5R
I/01R
I/O3R
I/O2R
GND
VCC
GND
I/O2L
VCC
I/O4R
I/O0L
I/O1L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
I/O8L
GND
I/O0R
3332313029282726
CY7C019 (128K x 9)
100-Pin TQFP
(Top View)
[6]
[6]

CY7C018-15AC

Mfr. #:
Manufacturer:
Cypress Semiconductor
Description:
IC SRAM 576K PARALLEL 100TQFP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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