CAT872-30ULGT3 Datasheet CAT872-30ULGT3, CAT872-50ULGT3 | P1-P3

November, 2011 − Rev. 0

1 Publication Order Number:

CAT871/D

CAT871, CAT872

Dual Input Reset Generator

Description

CAT871, CAT872 are dual input reset generators designed to restart

microprocessor and microcontroller based systems when the

watchdog timer or other resetting mechanisms have become disabled

or failed.

CAT871, CAT872 monitor two inputs and output an active low reset

pulse after both inputs have been active (logic low) for a factory preset

minimum time. The reset pulse width is 2.2 ms for CAT871 and 70 ms

for CAT872. Releasing either input from its active state before the

minimum timeout period resets the internal timer and both inputs must

return to being active before the timer will restart with a fresh count

down.

CAT871, CAT872’s open drain output is capable of sinking up to

3 mA of current and may be wire−OR’d with other open drain devices

to drive a common reset input.

Features

• Operate on 1.65 V to 5.5 V Power Supplies

• Ultra Low Quiescent Current: 10 nA (typical)

• Schmitt Trigger Inputs

• 8 Factory Preset Delay Times from 0.5 s to 5 s to Choose From

• Small mLLGA−6 Package: 1.45 x 1.0 x 0.4 mm

• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS

Compliant

Typical Applications

• Mobile Phones

• PDAs

• MP3 Players

• Personal Navigation Devices

Figure 1. Application Schematic

http://onsemi.com

PIN CONNECTIONS

ULLGA−6

UL SUFFIX

CASE 613AF

MARKING DIAGRAM

(Top View)

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

ORDERING INFORMATION

VDD

RESET

GND

MR1

MR2

NIC

X = Specific Device Code

X = (J = CAT871, K = CAT872)

M = Date Code

CAT871, CAT872

http://onsemi.com

FUNCTIONAL BLOCK DIAGRAM

RESET

Pulse

Generator

VDD

MR2

MR1

GND

Delay Timer

Figure 2. Functional Block Diagram

RESET

Table 1. PIN FUNCTION DESCRIPTION

Pin No. Pin Name Description

1 MR1 Manual reset input #1. CMOS input.

2 MR2 Manual reset input #2. CMOS input.

3 NIC No Internal Connection. A voltage or signal applied to this pin will have no effect on device operation.

4 GND System Ground.

5 RESET Reset Output. Active−low open drain output.

6 VDD Positive Power Supply.

Table 2. ABSOLUTE MAXIMUM RATINGS

Rating Symbol Value Unit

Input Voltage Range V

−0.3 to 6 V

Output Voltage Range V

OUT

−0.3 to 6

or (V

+ 0.3), whichever is lower

Input Voltage; MR2, MR1 V

−0.3 to 6

or (V

+ 0.3), whichever is lower

Maximum Junction Temperature T

J(max)

150 °C

Output Current; RESET I

OUT

10 mA

Storage Temperature Range T

STG

−65 to 150 °C

ESD Capability, Human Body Model (Note 1) ESD

HBM

2 kV

ESD Capability, Machine Model (Note 1) ESD

200 V

Lead Temperature Soldering

Reflow (SMD Styles Only), Pb−Free Versions (Note 2)

SLD

260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. This device series incorporates ESD protection and is tested by the following methods:

ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)

ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)

Latch−up Current Maximum Rating: ≤150 mA per JEDEC standard: JESD78

2. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D

CAT871, CAT872

http://onsemi.com

Table 3. RECOMMENDED OPERATING CONDITIONS

Rating Symbol Min Max Unit

Input Voltage; VDD V

1.65 5.5 V

Input Voltage; MR1, MR2 V

0 V

Output Current; RESET I

OUT

0 3 mA

Ambient Temperature T

−40 85 °C

Table 4. ELECTRICAL OPERATING CHARACTERISTICS

= 1.65 V to 5.5 V. For typical values T

= 25°C, for min/max values T

= −40°C to +85°C unless otherwise noted.)

Parameter

Test Conditions Symbol Min Typ Max Unit

POWER

Supply Voltage V

1.65 5.5 V

Quiescent Supply Current MR1 = MR2 = V

10 1000 nA

Operating Supply Current MR1 = MR2 = 0 V

Measured during setup period. Measurement

includes current through internal 200 kΩ

pull−up resistor on MR2

LOGIC INPUTS AND OUTPUTS

Input Voltage; HIGH

MR1, MR2 V

0.7 x V

Input Voltage; LOW MR1, MR2 V

0.25xV

Hysteresis V

HYS

− 250 mV

Input Current MR1 = 0 V; V

= 5 V (no internal pull−up) I

50 300 nA

Input Current MR2 = 0 V; V

= 5 V

(internal 200 kW pull−up resistor)

Output Voltage; HIGH

External 10 kW pull−up resistor to V

– 0.1 V

Output Voltage; LOW I

SINK

= 3 mA, V

= 1.8 V V

0.1 0.4 V

TIMING

Timeout

CAT87x−05

LOW_DELAY

0.41 0.50 0.59 s

CAT87x−10 0.82 1.00 1.18 s

CAT87x−15 1.23 1.50 1.77 s

CAT87x−20 1.64 2.00 2.36 s

CAT87x−25 2.05 2.50 2.95 s

CAT87x−30 2.46 3.00 3.54 s

CAT87x−40 3.28 4.00 4.72 s

CAT87x−50 4.1 5.00 5.9 s

Reset Output Pulse Width

CAT871

1.8 2.2 2.6

CAT872 57 70 83

TEST MODE (at T

= 25°C) (Note 3)

Start TEST window

Test Mode delay MR1=0 V, MR2→8 cycles, delay measured

after 8

rising edge of the MR2 clock pulse

250

Test Mode Clock Frequency Clock applied to MR2 f

1 MHz

MR2 Test mode clock setup

time

Measured from MR1 falling edge to first

falling edge of MR2

MR2 Input Voltage; LOW MR2, Test mode operation V

IL_TM

0.2xV

MR2 Pulse Width t

500 ns

3. “Test Mode” parameters are not tested in production.

P1-P3 P4-P6 P7-P9

CAT872-30ULGT3

Mfr. #:

Buy CAT872-30ULGT3

Manufacturer:

ON Semiconductor

Description:

Supervisory Circuits 2 INPUT RESET IC

Lifecycle:

New from this manufacturer.

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CAT872-30ULGT3

CAT872-30ULGT3

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