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71V25761S166PFGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
6.42
IDT71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
7
Pin Configuration – 128K x 36, 165 fBGA
NOTES:
1. H1 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected.
2. These pins are NC for the "S" version or the JTAG signal listed for the "SA" version. Note: If NC, these pins can either be tied to VSS, VDD or left floating.
3. H11 can be left unconnected and the device will always remain in active mode.
4. Pins P11, N6, B11, A1, R2 and P2 are reserved for 9M, 18M, 36M, 72M, 144M and 288M respectively.
5. TRST is offered as an optional JTAG Reset if required in the application. If not needed, can be left floating and will internally be pulled to VDD.
1234567891011
ANC
(4)
A
7
CE
1
BW
3
BW
2
CS
1
BWE ADSC ADV
A
8
NC
BNC A
6
CS
0
BW
4
BW
1
CLK
GW OE ADSP
A
9
NC
(4)
CI/O
P3
NC V
DDQ
V
SS
V
SS
V
SS
V
SS
V
SS
V
DDQ
NC I/O
P2
DI/O
17
I/O
16
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
15
I/O
14
EI/O
19
I/O
18
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
13
I/O
12
FI/O
21
I/O
20
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
11
I/O
10
GI/O
23
I/O
22
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
9
I/O
8
HV
DD
(1)
NC NC V
DD
V
SS
V
SS
V
SS
V
DD
NC NC ZZ
(3)
JI/O
25
I/O
24
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
7
I/O
6
KI/O
27
I/O
26
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
5
I/O
4
LI/O
29
I/O
28
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
3
I/O
2
MI/O
31
I/O
30
V
DDQ
V
DD
V
SS
V
SS
V
SS
V
DD
V
DDQ
I/O
1
I/O
0
NI/O
P4
NC V
DDQ
V
SS
NC/ TRST
(2, 5)
NC
(4)
NC V
SS
V
DDQ
NC I/O
P1
PNCNC
(4)
A
5
A
2
NC/TDI
(2)
A
1
NC/TDO
(2)
A
10
A
13
A
14
NC
(4)
R
LBO
NC
(4)
A
4
A
3
NC/TMS
(2)
A
0
NC/TCK
(2)
A
11
A
12
A
15
A
16
5297 tbl 17
6.42
8
IDT71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test LoadAC Test Conditions
(VDDQ = 2.5V)
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
V
DDQ
/2
50Ω
I/O
Z
0
=50Ω
5297 drw 06
,
1
2
3
4
20 30 50 100 200
ΔtCD
(Typical, ns)
Capacitance (pF)
80
5
6
5297 drw 07
,
Symbol Parameter Test Conditions Min. Max. Unit
|I
LI
| Input Leakage Current V
DD
= Max., V
IN
= 0V to V
DD
___
5µA
|I
LZZ
|
ZZ, LBO and JTAG Input Leakage Current
(1 )
V
DD
= Max., V
IN
= 0V to V
DD
___
30 µA
|I
LO
| Output Leakage Current V
OUT
= 0V to V
DDQ
, Device Deselected
___
5µA
V
OL
Output Low Voltage I
OL
= +6mA, V
DD
= Min.
___
0.4 V
V
OH
Output High Voltage I
OH
= -6mA, V
DD
= Min. 2.0
___
V
5297 tbl 08
Symbol Parameter Test Conditions
200MHz 183MHz 166MHz
UnitCom'l Only Com'l Ind Com'l Ind
I
DD
Operating Power Supply
Current
Device Selected, Outputs Open, VDD = Max.,
V
DDQ = Max., VIN > VIH or < VIL, f = fMAX
(2 )
360 340 350 320 330 mA
I
SB1 CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
V
DDQ = Max., VIN > VHD or < VLD, f = 0
(2,3)
30 30 35 30 35 mA
I
SB2 Clock Running Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
V
DDQ = Max., VIN > VHD or < VLD, f = fMAX
(2,3)
130 120 130 110 120 mA
I
ZZ
Full Sleep Mode Supply
Current
ZZ >
VHD, VDD = Max.
30 30 35 30 35 mA
5297 tbl 09
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
0 to 2.5V
2ns
(V
DDQ
/2)
(V
DDQ
/2)
See Figure 1
5297 tbl 10
NOTE:
1. The LBO, TMS, TDI, TCK and TRST pins will be internally pulled to VDD and the ZZ pin will be internally pulled to VSS if they are not actively driven in the application.
6.42
IDT71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
9
Synchronous Truth Table
(1,3)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. OE is an asynchronous input.
3. ZZ = low for this table.
Operation Address
Used
CE
CS
0
CS
1
ADSP ADSC ADV GW BWE BWx OE
(2)
CLK I/O
Deselected Cycle, Power Down None H X X X L X X X X X - HI-Z
Deselected Cycle, Power Down None L X H L X X X X X X - HI-Z
Deselected Cycle, Power Down None L L X L X X X X X X - HI-Z
Deselected Cycle, Power Down None L X H X L X X X X X - HI-Z
Deselected Cycle, Power Down None L L X X L X X X X X - HI-Z
Read Cycle, Begin Burst External L H L L X X X X X L - D
OUT
Read Cycle, Begin Burst External L H L L X X X X X H - HI-Z
Read Cycle, Begin Burst External L H L H L X H H X L - D
OUT
Read Cycle, Begin Burst External L H L H L X H L H L - D
OUT
Read Cycle, Begin Burst External L H L H L X H L H H - HI-Z
Write Cycle, Begin Burst External L H L H L X H L L X - D
IN
Write Cycle, Begin Burst External L H L H L X L X X X - D
IN
Read Cycle, Continue Burst Next X X X H H L H H X L - D
OUT
Read Cycle, Continue Burst Next X X X H H L H H X H - HI-Z
Read Cycle, Continue Burst Next X X X H H L H X H L - D
OUT
Read Cycle, Continue Burst Next X X X H H L H X H H - HI-Z
Read Cycle, Continue Burst Next H X X X H L H H X L - D
OUT
Read Cycle, Continue Burst Next H X X X H L H H X H - HI-Z
Read Cycle, Continue Burst Next H X X X H L H X H L - D
OUT
Read Cycle, Continue Burst Next H X X X H L H X H H - HI-Z
Write Cycle, Continue Burst Next X X X H H L H L L X - D
IN
Write Cycle, Continue Burst Next X X X H H L L X X X - D
IN
Write Cycle, Continue Burst Next H X X X H L H L L X - D
IN
Write Cycle, Continue Burst Next H X X X H L L X X X - D
IN
Read Cycle, Suspend Burst Current X X X H H H H H X L - D
OUT
Read Cycle, Suspend Burst Current X X X H H H H H X H - HI-Z
Read Cycle, Suspend Burst Current X X X H H H H X H L - D
OUT
Read Cycle, Suspend Burst Current X X X H H H H X H H - HI-Z
Read Cycle, Suspend Burst Current H X X X H H H H X L - D
OUT
Read Cycle, Suspend Burst Current H X X X H H H H X H - HI-Z
Read Cycle, Suspend Burst Current H X X X H H H X H L - D
OUT
Read Cycle, Suspend Burst Current H X X X H H H X H H - HI-Z
Write Cycle, Suspend Burst Current X X X H H H H L L X - D
IN
Write Cycle, Suspend Burst Current X X X H H H L X X X - D
IN
Write Cycle, Suspend Burst Current H X X X H H H L L X - D
IN
Write Cycle, Suspend Burst Current H X X X H H L X X X - D
IN
5297 tbl 11
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

71V25761S166PFGI8

Mfr. #:
Buy 71V25761S166PFGI8
Manufacturer:
IDT
Description:
SRAM 4Mb PBSRAM 128K x 36 w/2.5V I/O Pipeline
Lifecycle:
New from this manufacturer.
Delivery:
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