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IDT71V25761YS200PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
6.42
10
IDT71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 00011011
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1 )
11100100
5297 tbl 14
Linear Burst Sequence Table (LBO=VSS)
Synchronous Write Function Truth Table
(1)
Asynchronous Truth Table
(1)
Interleaved Burst Sequence Table (LBO=VDD)
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
3. Multiple bytes may be selected during the same cycle.
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
Operation
GW BWE BW
1
BW
2
BW
3
BW
4
Read HHXXXX
Read HLHHHH
Write all BytesLXXXXX
Write all Bytes H L L L L L
Write Byte 1
(3 )
HLLHHH
Write Byte 2
(3 )
HLHLHH
Write Byte 3
(3 )
HLHHLH
Write Byte 4
(3 )
HLHHHL
5297 tbl 12
Sequence 1 Sequence 2 Sequence 3 Sequence 4
A1 A0 A1 A0 A1 A0 A1 A0
First Address 00011011
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address
(1 )
11000110
5297 tbl 15
Operation
(2 )
OE
ZZ I/O Status Power
Read L L Data Out Active
Read H L High-Z Active
Write X L High-Z – Data In Active
Deselected X L High-Z Standby
Sleep Mode X H High-Z Sleep
5297 tbl 13
6.42
IDT71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
11
AC Electrical Characteristics
(VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above VIH and LOW below VIL.
2. Transition is measured ±200mV from steady-state.
3. Device must be deselected when powered-up from sleep mode.
4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation.
5. Commercial temperature range only.
200MHz
(5)
183MHz 166MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
t
CY C
Clock Cycle Time 5
____
5.5
____
6
____
ns
t
CH
(1)
Clock High Pulse Width 2
____
2.2
____
2.4
____
ns
t
CL
(1)
Clock Low Pulse Width 2
____
2.2
____
2.4
____
ns
Output Parameters
t
CD
Clock High to Valid Data
____
3.1
____
3.3
____
3.5 ns
t
CDC
Clock High to Data Change 1.0
____
1.0
____
1.0
____
ns
t
CL Z
(2)
Clock High to Output Active 0
____
0
____
0
____
ns
t
CHZ
(2 )
Clock High to Data High-Z 1.5 3.1 1.5 3.3 1.5 3.5 ns
t
OE
Output Enable Access Time
____
3.1
____
3.3
____
3.5 ns
t
OLZ
(2)
Output Enable Low to Output Active 0
____
0
____
0
____
ns
t
OHZ
(2)
Output Enable High to Output High-Z
____
3.1
____
3.3
____
3.5 ns
Set Up Times
t
SA
Address Setup Time 1.2
____
1.5
____
1.5
____
ns
t
SS
Address Status Setup Time 1.2
____
1.5
____
1.5
____
ns
t
SD
Data In Setup Time 1.2
____
1.5
____
1.5
____
ns
t
SW
Write Setup Time 1.2
____
1.5
____
1.5
____
ns
t
SAV
Address Advance Setup Time 1.2
____
1.5
____
1.5
____
ns
t
SC
Chip Enable/Select Setup Time 1.2
____
1.5
____
1.5
____
ns
Hold Times
t
HA
Address Hold Time 0.4
____
0.5
____
0.5
____
ns
t
HS
Address Status Hold Time 0.4
____
0.5
____
0.5
____
ns
t
HD
Data In Hold Time 0.4
____
0.5
____
0.5
____
ns
t
HW
Write Hold Time 0.4
____
0.5
____
0.5
____
ns
t
HAV
Address Advance Hold Time 0.4
____
0.5
____
0.5
____
ns
t
HC
Chip Enable/Select Hold Time 0.4
____
0.5
____
0.5
____
ns
Sleep Mode and Configuration Parameters
t
ZZPW
ZZ Pulse Width 100
____
100
____
100
____
ns
t
ZZR
(3)
ZZ Recovery Time 100
____
100
____
100
____
ns
t
CFG
(4)
Configuration Set-up Time 20
____
22
____
24
____
ns
4876 tbl 16
6.42
12
IDT71V25761 128K x 36, 3.3V Synchronous SRAMs with
2.5V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
NOTES:
1. O1 (Ax) represents the first output from the external address Ax. O1 (Ay) represents the first output from the external address Ay; O2 (Ay) represents the next output data in the burst sequence
of the base address Ay, etc. where A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. ZZ input is LOW and LBO is Don't Care for this cycle.
3. CS
0 timing transitions are identical but inverted to the CE and CS1 signals. For example, when CE and CS1 are LOW on this waveform, CS0 is HIGH.
Timing Waveform of Pipeline Read Cycle
(1,2)
t
C
H
Z
t
S
A
t
S
C
t
H
S
G
W
,
B
W
E
,
B
W
x
t
S
W
t
C
L
t
S
A
V
t
H
W
t
H
A
V
C
L
K
A
D
S
C
(
1
)
A
D
D
R
E
S
S
t
C
Y
C
t
C
H
t
H
A
t
H
C
t
O
E
t
O
H
Z
O
E
t
C
D
t
O
L
Z
O
1
(
A
x
)
D
A
T
A
O
U
T
t
C
D
C
O
1
(
A
y
)
O
3
(
A
y
)
O
2
(
A
y
)
O
2
(
A
y
)
t
C
L
Z
A
D
V
C
E
,
C
S
1
(
N
o
t
e
3
)
P
i
p
e
l
i
n
e
d
R
e
a
d
B
u
r
s
t
P
i
p
e
l
i
n
e
d
R
e
a
d
O
u
t
p
u
t
D
i
s
a
b
l
e
d
A
x
A
y
t
S
S
O
1
(
A
y
)
(
B
u
r
s
t
w
r
a
p
s
a
r
o
u
n
d
t
o
i
t
s
i
n
i
t
i
a
l
s
t
a
t
e
)
O
4
(
A
y
)
5
2
9
7
d
r
w
0
8
A
D
S
P
A
D
V
H
I
G
H
s
u
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p
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,
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

IDT71V25761YS200PF8

Mfr. #:
Buy IDT71V25761YS200PF8
Manufacturer:
Description:
IC SRAM 4.5M PARALLEL 100TQFP
Lifecycle:
New from this manufacturer.
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