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FM22LD16-55-BGTR
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P22
FM22LD16
Document Number: 001-86190 Rev
.
*E
Page 16 of 22
Power Cycle and Sleep Mode Timing
Over the
Oper
ating
Range
Parameter
Description
Min
Max
Unit
t
PU
Power-up (after V
DD
min. is reached) to first access time
450
–
µs
t
PD
Last write (WE
HIGH) to power down time
0
–
µs
t
VR
[12, 13]
V
DD
power-up ramp rate
50
–
µs/V
t
VF
[12, 13]
V
DD
power-down ramp rate
100
–
µs/V
Figure 15. Power Cycle and Sleep
Mode Timing
V
DD
t
VF
V
DD
min
min
V
DD
t
VR
t
PU
t
PD
Access Allo
wed
Note
12.
Slope measured at any point on the V
DD
waveform.
13.
Cypress cannot test
or characterize all V
DD
power ramp profiles. The behavior of t
he inte
rnal circuit
s is difficu
lt to predict when V
DD
is below the
level of a tra
nsistor
threshold voltage
. Cypress strongly recommends that V
DD
power up faster than 100 ms throug
h the range of 0.4 V to 1.0 V
.
FM22LD16
Document Number: 001-86190 Rev
.
*E
Page 17 of 22
Functional T
ruth T
able
CE
WE
A
17-2
A
1-0
Operation
[14, 15]
H
X
X
X
S
tandby/Idle
↓
L
H
H
V
V
V
V
Read
L
H
No Change
Change
Page Mode Read
L
H
C
hange
V
Random Read
↓
L
L
L
V
V
V
V
CE
-Controlled Write
[15]
L
↓
VV
W
E
-Controlled Write
[15, 16]
L
↓
No Change
V
Page Mode Write
[17]
↑
L
X
X
X
X
X
X
S
t
arts pre-charge
Notes
14.
H = Logic HIGH, L = Logic LOW
, V = V
alid Data, X = Don't Care,
↓
= toggle LOW
,
↑
= toggle HIGH.
15.
For write cycles, data-in is latched on the rising edge of CE
or WE
, whichever comes first.
16.
WE
-controlled write cycle begins as a Read cycle and then A
17-2
is latched.
17.
Addresses A
1-0
must remain stable fo
r at least 10 ns during page mode oper
ation.
18.
The UB
and LB
pins may be groun
ded if 1) the system does not perf
orm byte writes and 2) the devi
ce is not configured as a 512 K x 8.
FM22LD16
Document Number: 001-86190 Rev
.
*E
Page 18 of 22
Ordering Code Definitions
Ordering Information
Access time (ns)
Ordering Co
de
Package Diagra
m
Package T
ype
Operating Range
55
FM22LD16-55-BG
001-91
15
8
48-ball FBGA
Industrial
FM22LD16-55-BGTR
All the above part
s are Pb-free.
Option:
blank = S
tandard; TR = T
a
pe and Reel
Package T
ype:
BG = 48-ball FBGA
Access T
ime: 55 ns
I/O Widt
h: × 16
V
ol
tage: 2.7 V to 3.6 V
4-Mbit Para
llel F-RAM
Cypress
22
FM
LD
16 -
55 -
BG
TR
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
P19-P21
P22-P22
FM22LD16-55-BGTR
Mfr. #:
Buy FM22LD16-55-BGTR
Manufacturer:
Cypress Semiconductor
Description:
F-RAM 4M (256Kx16) 55ns F-RAM
Lifecycle:
New from this manufacturer.
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Products related to this Datasheet
FM22LD16-55-BG
FM22LD16-55-BGTR