Lattice Semiconductor LA-ispMACH 4000V/Z Automotive Family Data Sheet
21
LA-ispMACH 4000V/Z Internal Timing Parameters
Over Recommended Operating Conditions
Parameter Description
LA-ispMACH 4000V
-75
LA-ispMACH 4000Z
-75
UnitsMin. Max. Min. Max.
In/Out Delays
t
IN
Input Buffer Delay — 1.50 — 1.80 ns
t
GOE
Global OE Pin Delay — 6.04 — 4.30 ns
t
GCLK_IN
Global Clock Input Buffer Delay — 2.28 — 2.15 ns
t
BUF
Delay through Output Buffer — 1.50 — 1.30 ns
t
EN
Output Enable Time — 0.96 — 2.70 ns
t
DIS
Output Disable Time — 0.96 — 2.70 ns
Routing/GLB Delays
t
ROUTE
Delay through GRP — 2.26 — 2.50 ns
t
MCELL
Macrocell Delay — 1.45 — 1.00 ns
t
INREG
Input Buffer to Macrocell Register Delay — 0.96 — 1.00 ns
t
FBK
Internal Feedback Delay — 0.00 — 0.05 ns
t
PDb
5-PT Bypass Propagation Delay — 2.24 — 1.90 ns
t
PDi
Macrocell Propagation Delay — 1.24 — 1.00 ns
Register/Latch Delays
t
S
D-Register Setup Time (Global Clock) 1.57 — 1.35 — ns
t
S_PT
D-Register Setup Time (Product Term Clock) 1.32 — 2.45 — ns
t
ST
T-Register Setup Time (Global Clock) 1.77 — 1.55 — ns
t
ST_PT
T-Register Setup Time (Product Term Clock) 1.32 — 2.75 — ns
t
H
D-Register Hold Time 2.93 — 3.15 — ns
t
HT
T-Register Hold Time 2.93 — 3.15 — ns
t
SIR
D-Input Register Setup Time (Global Clock) 1.57 — 0.75 — ns
t
SIR_PT
D-Input Register Setup Time (Product Term
Clock)
1.45 —
1.45 —
ns
t
HIR
D-Input Register Hold Time (Global Clock) 1.18 — 1.95 — ns
t
HIR_PT
D-Input Register Hold Time (Product Term
Clock)
1.18 —
1.18 —
ns
t
COi
Register Clock to Output/Feedback MUX Time — 0.67 — 1.05 ns
t
CES
Clock Enable Setup Time 2.25 — 2.00 — ns
t
CEH
Clock Enable Hold Time 1.88 — 0.00 — ns
t
SL
Latch Setup Time (Global Clock) 1.57 — 1.65 — ns
t
SL_PT
Latch Setup Time (Product Term Clock) 1.32 — 2.15 — ns
t
HL
Latch Hold Time 1.17 — 1.17 — ns
t
GOi
Latch Gate to Output/Feedback MUX Time — 0.33 — 0.33 ns
t
PDLi
Propagation Delay through Transparent Latch to
Output/Feedback MUX
— 0.25
— 0.25
ns
t
SRi
Asynchronous Reset or Set to Output/Feedback
MUX Delay
0.28 —
— 0.28
ns
t
SRR
Asynchronous Reset or Set Recovery Time 1.67 — — 1.67 ns
Control Delays
t
BCLK
GLB PT Clock Delay — 1.12 — 1.25 ns
t
PTCLK
Macrocell PT Clock Delay — 0.87 — 1.25 ns