10
LT1398/LT1399/LT1399HV
sn13989 13989fas
U
S
A
O
PP
L
IC
AT
I
WU
U
I FOR ATIO
Power Supplies
The LT1398/LT1399 will operate from single or split
supplies from ±2V (4V total) to ±6V (12V total). The
LT1399HV will operate from single or split supplies from
±2V (4V total) to ±7.5V (15V total). It is not necessary to
use equal value split supplies, however the offset voltage
and inverting input bias current will change. The offset
voltage changes about 600µV per volt of supply mis-
match. The inverting bias current will typically change
about 2µA per volt of supply mismatch.
Slew Rate
Unlike a traditional voltage feedback op amp, the slew rate
of a current feedback amplifier is not independent of the
amplifier gain configuration. In a current feedback ampli-
fier, both the input stage and the output stage have slew rate
limitations. In the inverting mode, and for gains of 2 or more
in the noninverting mode, the signal amplitude between the
input pins is small and the overall slew rate is that of the
output stage. For gains less than 2 in the noninverting mode,
the overall slew rate is limited by the input stage.
The input slew rate of the LT1398/LT1399/LT1399HV is
approximately 600V/µs and is set by internal currents and
capacitances. The output slew rate is set by the value of the
feedback resistor and internal capacitance. At a gain of 2
with 324Ω feedback and gain resistors and ±5V supplies,
the output slew rate is typically 800V/µs. Larger feedback
resistors will reduce the slew rate as will lower supply
voltages.
Enable/ Disable
Each amplifier of the LT1398/LT1399/LT1399HV has a
unique high impedance, zero supply current mode which
is controlled by its own EN pin. These amplifiers are
designed to operate with CMOS logic; the amplifiers draw
zero current when these pins are high. To activate each
amplifier, its EN pin is normally pulled to a logic low.
However, supply current will vary as the voltage between
the V
+
supply and EN is varied. As seen in Figure 1, +I
S
does vary with (V
+
– V
EN
), particularly when the voltage
difference is less than 3V. For normal operation, it is
important to keep the EN pin at least 3V below the V
+
supply. If a V
+
of less than 3V is desired, and the amplifier
will remain enabled at all times, then the EN pin should be
tied to the V
–
supply. The enable pin current is approxi-
mately 30µA when activated. If using CMOS open-drain
logic, an external 1k pull-up resistor is recommended to
ensure that the LT1399 remains disabled in spite of any
CMOS drain-leakage currents.
Figure 1. +I
S
vs (V
+
– V
EN
)
V
+
– V
EN
(V)
0
0
+I
S
(mA)
0.5
1.5
2.0
2.5
5.0
3.5
2
4
5
1398/99 F01
1.0
4.0
4.5
3.0
1
3
6
7
T
A
= 25°C
V
+
= 5V
V
–
= –5V
V
–
= 0V
Figure 2. Amplifier Enable Time, A
V
= 2
V
S
= ±5V
V
IN
= 1V
R
F
= 324Ω
R
G
= 324Ω
R
L
= 100Ω
1398/99 F02
OUTPUT
EN
Figure 3. Amplifier Disable Time, A
V
= 2
V
S
= ±5V
V
IN
= 1V
R
F
= 324Ω
R
G
= 324Ω
R
L
= 100Ω
1398/99 F03
OUTPUT
EN
